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This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module. DDR2 controller operates in half-rate mode (upto 533MHZ frequency). Signed-off-by: Paul Thacker <paul.thacker@microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
33 lines
894 B
C
33 lines
894 B
C
/*
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* (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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*/
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#ifndef __MICROCHIP_PIC32_DDR_H
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#define __MICROCHIP_PIC32_DDR_H
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/* called by initdram() function */
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void ddr2_phy_init(void);
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void ddr2_ctrl_init(void);
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phys_size_t ddr2_calculate_size(void);
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/* Maximum number of agents */
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#define NUM_AGENTS 5
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/* Board can provide agent specific parameters for arbitration by
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* filling struct ddr2_arbiter_params for all the agents and
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* implementing board_get_ddr_arbiter_params() to return the filled
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* structure.
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*/
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struct ddr2_arbiter_params {
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u32 min_limit; /* min bursts to execute per arbitration */
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u32 req_period; /* request period threshold for accepted cmds */
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u32 min_cmd_acpt; /* min number of accepted cmds */
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};
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const struct ddr2_arbiter_params *board_get_ddr_arbiter_params(void);
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#endif /* __MICROCHIP_PIC32_DDR_H */
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