mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-07 18:53:45 +09:00
d5cc3f5241
This patch adds support for the CPLD GPIO bus found on some LaCie boards (as the 2Big/5Big Network v2 and the 2Big NAS). This parallel GPIO bus exposes two registers (address and data). Each of this register is made up of several dedicated GPIOs. An extra GPIO is used to notify the CPLD that the registers have been updated. Mostly this bus is used to configure the LEDs on LaCie boards. Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
25 lines
643 B
C
25 lines
643 B
C
/*
|
|
* Copyright (C) 2013 Simon Guinot <simon.guinot@sequanux.org>
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of
|
|
* the License, or (at your option) any later version.
|
|
*/
|
|
|
|
#ifndef _LACIE_CPLD_GPI0_BUS_H
|
|
#define _LACIE_CPLD_GPI0_BUS_H
|
|
|
|
struct cpld_gpio_bus {
|
|
unsigned *addr;
|
|
unsigned num_addr;
|
|
unsigned *data;
|
|
unsigned num_data;
|
|
unsigned enable;
|
|
};
|
|
|
|
void cpld_gpio_bus_write(struct cpld_gpio_bus *cpld_gpio_bus,
|
|
unsigned addr, unsigned value);
|
|
|
|
#endif /* _LACIE_CPLD_GPI0_BUS_H */
|