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https://github.com/brain-hackers/u-boot-brain
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62b2bb5374
Import the RCar Gen3 DTS and headers from upstream Linux kernel v4.14, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . This includes both M3 and H3 ULCB and Salvator-X boards. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
86 lines
1.3 KiB
Plaintext
86 lines
1.3 KiB
Plaintext
/*
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* Device Tree Source for the Eagle board
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*
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* Copyright (C) 2016-2017 Renesas Electronics Corp.
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* Copyright (C) 2017 Cogent Embedded, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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/dts-v1/;
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#include "r8a77970.dtsi"
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/ {
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model = "Renesas Eagle board based on r8a77970";
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compatible = "renesas,eagle", "renesas,r8a77970";
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aliases {
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serial0 = &scif0;
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ethernet0 = &avb;
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};
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chosen {
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
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stdout-path = "serial0:115200n8";
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};
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memory@48000000 {
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device_type = "memory";
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/* first 128MB is reserved for secure area. */
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reg = <0x0 0x48000000 0x0 0x38000000>;
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};
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};
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&extal_clk {
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clock-frequency = <16666666>;
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};
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&extalr_clk {
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clock-frequency = <32768>;
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};
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&pfc {
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pinctrl-0 = <&scif_clk_pins>;
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pinctrl-names = "default";
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scif0_pins: scif0 {
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groups = "scif0_data";
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function = "scif0";
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};
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scif_clk_pins: scif_clk {
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groups = "scif_clk_b";
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function = "scif_clk";
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};
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avb_pins: avb {
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groups = "avb0_mdc";
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function = "avb0";
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};
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};
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&scif0 {
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pinctrl-0 = <&scif0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&scif_clk {
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clock-frequency = <14745600>;
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status = "okay";
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};
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&avb {
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pinctrl-0 = <&avb_pins>;
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pinctrl-names = "default";
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renesas,no-ether-link;
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phy-handle = <&phy0>;
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status = "okay";
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phy0: ethernet-phy@0 {
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rxc-skew-ps = <1500>;
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reg = <0>;
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};
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};
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