mirror of
https://github.com/brain-hackers/u-boot-brain
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176 lines
4.0 KiB
C
176 lines
4.0 KiB
C
/*
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* (C) Copyright 2009
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _IMXIMAGE_H_
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#define _IMXIMAGE_H_
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#define MAX_HW_CFG_SIZE_V2 121 /* Max number of registers imx can set for v2 */
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#define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */
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#define APP_CODE_BARKER 0xB1
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#define DCD_BARKER 0xB17219E9
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/*
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* NOTE: This file must be kept in sync with arch/arm/include/asm/\
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* imx-common/imximage.cfg because tools/imximage.c can not
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* cross-include headers from arch/arm/ and vice-versa.
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*/
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#define CMD_DATA_STR "DATA"
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/* Initial Vector Table Offset */
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#define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
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#define FLASH_OFFSET_STANDARD 0x400
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#define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD
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#define FLASH_OFFSET_SD FLASH_OFFSET_STANDARD
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#define FLASH_OFFSET_SPI FLASH_OFFSET_STANDARD
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#define FLASH_OFFSET_ONENAND 0x100
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#define FLASH_OFFSET_NOR 0x1000
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#define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD
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/* Initial Load Region Size */
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#define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF
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#define FLASH_LOADSIZE_STANDARD 0x1000
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#define FLASH_LOADSIZE_NAND FLASH_LOADSIZE_STANDARD
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#define FLASH_LOADSIZE_SD FLASH_LOADSIZE_STANDARD
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#define FLASH_LOADSIZE_SPI FLASH_LOADSIZE_STANDARD
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#define FLASH_LOADSIZE_ONENAND 0x400
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#define FLASH_LOADSIZE_NOR 0x0 /* entire image */
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#define FLASH_LOADSIZE_SATA FLASH_LOADSIZE_STANDARD
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#define IVT_HEADER_TAG 0xD1
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#define IVT_VERSION 0x40
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#define DCD_HEADER_TAG 0xD2
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#define DCD_COMMAND_TAG 0xCC
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#define DCD_VERSION 0x40
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#define DCD_COMMAND_PARAM 0x4
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enum imximage_cmd {
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CMD_INVALID,
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CMD_IMAGE_VERSION,
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CMD_BOOT_FROM,
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CMD_BOOT_OFFSET,
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CMD_DATA,
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CMD_CSF,
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};
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enum imximage_fld_types {
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CFG_INVALID = -1,
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CFG_COMMAND,
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CFG_REG_SIZE,
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CFG_REG_ADDRESS,
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CFG_REG_VALUE
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};
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enum imximage_version {
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IMXIMAGE_VER_INVALID = -1,
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IMXIMAGE_V1 = 1,
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IMXIMAGE_V2
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};
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typedef struct {
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uint32_t type; /* Type of pointer (byte, halfword, word, wait/read) */
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uint32_t addr; /* Address to write to */
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uint32_t value; /* Data to write */
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} dcd_type_addr_data_t;
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typedef struct {
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uint32_t barker; /* Barker for sanity check */
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uint32_t length; /* Device configuration length (without preamble) */
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} dcd_preamble_t;
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typedef struct {
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dcd_preamble_t preamble;
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dcd_type_addr_data_t addr_data[MAX_HW_CFG_SIZE_V1];
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} dcd_v1_t;
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typedef struct {
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uint32_t app_code_jump_vector;
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uint32_t app_code_barker;
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uint32_t app_code_csf;
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uint32_t dcd_ptr_ptr;
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uint32_t super_root_key;
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uint32_t dcd_ptr;
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uint32_t app_dest_ptr;
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} flash_header_v1_t;
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typedef struct {
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uint32_t length; /* Length of data to be read from flash */
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} flash_cfg_parms_t;
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typedef struct {
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flash_header_v1_t fhdr;
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dcd_v1_t dcd_table;
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flash_cfg_parms_t ext_header;
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} imx_header_v1_t;
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typedef struct {
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uint32_t addr;
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uint32_t value;
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} dcd_addr_data_t;
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typedef struct {
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uint8_t tag;
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uint16_t length;
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uint8_t version;
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} __attribute__((packed)) ivt_header_t;
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typedef struct {
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uint8_t tag;
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uint16_t length;
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uint8_t param;
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} __attribute__((packed)) write_dcd_command_t;
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typedef struct {
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ivt_header_t header;
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write_dcd_command_t write_dcd_command;
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dcd_addr_data_t addr_data[MAX_HW_CFG_SIZE_V2];
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} dcd_v2_t;
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typedef struct {
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uint32_t start;
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uint32_t size;
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uint32_t plugin;
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} boot_data_t;
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typedef struct {
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ivt_header_t header;
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uint32_t entry;
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uint32_t reserved1;
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uint32_t dcd_ptr;
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uint32_t boot_data_ptr;
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uint32_t self;
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uint32_t csf;
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uint32_t reserved2;
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} flash_header_v2_t;
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typedef struct {
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flash_header_v2_t fhdr;
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boot_data_t boot_data;
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dcd_v2_t dcd_table;
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} imx_header_v2_t;
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/* The header must be aligned to 4k on MX53 for NAND boot */
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struct imx_header {
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union {
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imx_header_v1_t hdr_v1;
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imx_header_v2_t hdr_v2;
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} header;
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};
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typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
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char *name, int lineno,
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int fld, uint32_t value,
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uint32_t off);
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typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
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uint32_t dcd_len,
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char *name, int lineno);
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typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
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uint32_t entry_point, uint32_t flash_offset);
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#endif /* _IMXIMAGE_H_ */
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