mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-28 13:53:44 +09:00
ec7113fbb4
The H2 Stout port was broken since some time. This patch updates the H2 Stout port to use modern frameworks, DM, DT probing, SPL and TPL for the preloading and puts it on par with the M2 Porter board. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
131 lines
2.7 KiB
C
131 lines
2.7 KiB
C
/*
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* board/renesas/stout/stout.c
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* This file is Stout board support.
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*
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* Copyright (C) 2015 Renesas Electronics Europe GmbH
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* Copyright (C) 2015 Renesas Electronics Corporation
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* Copyright (C) 2015 Cogent Embedded, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <malloc.h>
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#include <netdev.h>
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#include <dm.h>
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#include <dm/platform_data/serial_sh.h>
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#include <environment.h>
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#include <asm/processor.h>
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#include <asm/mach-types.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/arch/rmobile.h>
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#include <asm/arch/rcar-mstp.h>
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#include <asm/arch/mmc.h>
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#include <asm/arch/sh_sdhi.h>
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#include <miiphy.h>
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#include <i2c.h>
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#include <mmc.h>
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#include "qos.h"
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#include "cpld.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define CLK2MHZ(clk) (clk / 1000 / 1000)
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void s_init(void)
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{
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struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
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struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
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/* Watchdog init */
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writel(0xA5A5A500, &rwdt->rwtcsra);
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writel(0xA5A5A500, &swdt->swtcsra);
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/* CPU frequency setting. Set to 1.4GHz */
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if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
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u32 stat = 0;
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u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
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<< PLL0_STC_BIT;
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clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
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do {
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stat = readl(PLLECR) & PLL0ST;
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} while (stat == 0x0);
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}
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/* QoS(Quality-of-Service) Init */
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qos_init();
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}
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#define TMU0_MSTP125 BIT(25)
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#define SD2CKCR 0xE6150078
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#define SD2_97500KHZ 0x7
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int board_early_init_f(void)
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{
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/* TMU0 */
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mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
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/*
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* SD0 clock is set to 97.5MHz by default.
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* Set SD2 to the 97.5MHz as well.
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*/
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writel(SD2_97500KHZ, SD2CKCR);
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return 0;
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}
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#define ETHERNET_PHY_RESET 123 /* GPIO 3 31 */
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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cpld_init();
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/* Force ethernet PHY out of reset */
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gpio_request(ETHERNET_PHY_RESET, "phy_reset");
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gpio_direction_output(ETHERNET_PHY_RESET, 0);
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mdelay(20);
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gpio_direction_output(ETHERNET_PHY_RESET, 1);
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return 0;
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}
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int dram_init(void)
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{
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if (fdtdec_setup_memory_size() != 0)
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return -EINVAL;
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return 0;
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}
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int dram_init_banksize(void)
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{
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fdtdec_setup_memory_banksize();
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return 0;
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}
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/* Stout has KSZ8041NL/RNL */
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#define PHY_CONTROL1 0x1E
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#define PHY_LED_MODE 0xC0000
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#define PHY_LED_MODE_ACK 0x4000
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int board_phy_config(struct phy_device *phydev)
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{
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int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
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ret &= ~PHY_LED_MODE;
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ret |= PHY_LED_MODE_ACK;
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ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
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return 0;
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}
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const struct rmobile_sysinfo sysinfo = {
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CONFIG_ARCH_RMOBILE_BOARD_STRING
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};
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