mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-26 21:03:44 +09:00
ec60a279ec
Access the timestamp ref ctrl register only if runinng at el3 level otherwise just return. This change fixes the issue when CRL APB is marked as secure and accessing when not in el3 causes exception. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
481 lines
8.6 KiB
C
481 lines
8.6 KiB
C
/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <sata.h>
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#include <ahci.h>
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#include <scsi.h>
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#include <malloc.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <usb.h>
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#include <dwc3-uboot.h>
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#include <zynqmppl.h>
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#include <i2c.h>
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#include <g_dnl.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
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!defined(CONFIG_SPL_BUILD)
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static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
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static const struct {
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u32 id;
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u32 ver;
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char *name;
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} zynqmp_devices[] = {
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{
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.id = 0x10,
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.name = "3eg",
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},
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{
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.id = 0x10,
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.ver = 0x2c,
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.name = "3cg",
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},
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{
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.id = 0x11,
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.name = "2eg",
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},
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{
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.id = 0x11,
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.ver = 0x2c,
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.name = "2cg",
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},
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{
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.id = 0x20,
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.name = "5ev",
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},
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{
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.id = 0x20,
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.ver = 0x100,
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.name = "5eg",
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},
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{
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.id = 0x20,
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.ver = 0x12c,
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.name = "5cg",
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},
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{
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.id = 0x21,
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.name = "4ev",
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},
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{
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.id = 0x21,
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.ver = 0x100,
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.name = "4eg",
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},
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{
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.id = 0x21,
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.ver = 0x12c,
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.name = "4cg",
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},
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{
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.id = 0x30,
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.name = "7ev",
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},
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{
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.id = 0x30,
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.ver = 0x100,
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.name = "7eg",
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},
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{
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.id = 0x30,
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.ver = 0x12c,
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.name = "7cg",
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},
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{
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.id = 0x38,
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.name = "9eg",
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},
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{
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.id = 0x38,
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.ver = 0x2c,
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.name = "9cg",
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},
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{
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.id = 0x39,
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.name = "6eg",
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},
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{
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.id = 0x39,
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.ver = 0x2c,
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.name = "6cg",
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},
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{
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.id = 0x40,
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.name = "11eg",
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},
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{ /* For testing purpose only */
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.id = 0x50,
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.ver = 0x2c,
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.name = "15cg",
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},
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{
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.id = 0x50,
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.name = "15eg",
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},
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{
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.id = 0x58,
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.name = "19eg",
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},
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{
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.id = 0x59,
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.name = "17eg",
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},
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{
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.id = 0x61,
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.name = "21dr",
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},
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{
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.id = 0x63,
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.name = "23dr",
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},
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{
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.id = 0x65,
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.name = "25dr",
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},
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{
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.id = 0x64,
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.name = "27dr",
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},
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{
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.id = 0x60,
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.name = "28dr",
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},
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{
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.id = 0x62,
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.name = "29dr",
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},
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};
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#endif
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int chip_id(unsigned char id)
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{
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struct pt_regs regs;
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int val = -EINVAL;
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if (current_el() != 3) {
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regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
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regs.regs[1] = 0;
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regs.regs[2] = 0;
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regs.regs[3] = 0;
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smc_call(®s);
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/*
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* SMC returns:
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* regs[0][31:0] = status of the operation
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* regs[0][63:32] = CSU.IDCODE register
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* regs[1][31:0] = CSU.version register
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* regs[1][63:32] = CSU.IDCODE2 register
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*/
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switch (id) {
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case IDCODE:
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regs.regs[0] = upper_32_bits(regs.regs[0]);
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regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
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ZYNQMP_CSU_IDCODE_SVD_MASK;
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regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
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val = regs.regs[0];
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break;
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case VERSION:
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regs.regs[1] = lower_32_bits(regs.regs[1]);
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regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
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val = regs.regs[1];
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break;
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case IDCODE2:
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regs.regs[1] = lower_32_bits(regs.regs[1]);
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regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
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val = regs.regs[1];
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break;
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default:
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printf("%s, Invalid Req:0x%x\n", __func__, id);
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}
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} else {
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switch (id) {
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case IDCODE:
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val = readl(ZYNQMP_CSU_IDCODE_ADDR);
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val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
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ZYNQMP_CSU_IDCODE_SVD_MASK;
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val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
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break;
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case VERSION:
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val = readl(ZYNQMP_CSU_VER_ADDR);
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val &= ZYNQMP_CSU_SILICON_VER_MASK;
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break;
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default:
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printf("%s, Invalid Req:0x%x\n", __func__, id);
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}
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}
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return val;
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}
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#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
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!defined(CONFIG_SPL_BUILD)
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static char *zynqmp_get_silicon_idcode_name(void)
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{
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u32 i, id, ver;
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id = chip_id(IDCODE);
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ver = chip_id(IDCODE2);
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for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
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if (zynqmp_devices[i].id == id && zynqmp_devices[i].ver == ver)
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return zynqmp_devices[i].name;
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}
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return "unknown";
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}
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#endif
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int board_early_init_f(void)
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{
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#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
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zynqmp_pmufw_version();
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#endif
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#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
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psu_init();
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#endif
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return 0;
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}
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#define ZYNQMP_VERSION_SIZE 9
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int board_init(void)
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{
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printf("EL Level:\tEL%d\n", current_el());
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#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
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!defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
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defined(CONFIG_SPL_BUILD))
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if (current_el() != 3) {
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static char version[ZYNQMP_VERSION_SIZE];
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strncat(version, "zu", 2);
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zynqmppl.name = strncat(version,
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zynqmp_get_silicon_idcode_name(),
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ZYNQMP_VERSION_SIZE - 3);
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printf("Chip ID:\t%s\n", zynqmppl.name);
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fpga_init();
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fpga_add(fpga_xilinx, &zynqmppl);
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}
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#endif
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return 0;
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}
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int board_early_init_r(void)
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{
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u32 val;
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if (current_el() != 3)
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return 0;
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val = readl(&crlapb_base->timestamp_ref_ctrl);
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val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
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if (!val) {
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val = readl(&crlapb_base->timestamp_ref_ctrl);
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val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
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writel(val, &crlapb_base->timestamp_ref_ctrl);
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/* Program freq register in System counter */
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writel(zynqmp_get_system_timer_freq(),
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&iou_scntr_secure->base_frequency_id_register);
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/* And enable system counter */
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writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
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&iou_scntr_secure->counter_control_register);
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}
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return 0;
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}
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int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
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{
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#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
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defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
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defined(CONFIG_ZYNQ_EEPROM_BUS)
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i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
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if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
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CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
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ethaddr, 6))
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printf("I2C EEPROM MAC address read failed\n");
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#endif
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return 0;
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}
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#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
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int dram_init_banksize(void)
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{
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return fdtdec_setup_memory_banksize();
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}
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int dram_init(void)
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{
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if (fdtdec_setup_memory_size() != 0)
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return -EINVAL;
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return 0;
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}
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#else
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int dram_init(void)
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{
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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#endif
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void reset_cpu(ulong addr)
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{
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}
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int board_late_init(void)
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{
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u32 reg = 0;
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u8 bootmode;
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const char *mode;
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char *new_targets;
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int ret;
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if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
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debug("Saved variables - Skipping\n");
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return 0;
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}
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ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®);
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if (ret)
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return -EINVAL;
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if (reg >> BOOT_MODE_ALT_SHIFT)
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reg >>= BOOT_MODE_ALT_SHIFT;
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bootmode = reg & BOOT_MODES_MASK;
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puts("Bootmode: ");
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switch (bootmode) {
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case USB_MODE:
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puts("USB_MODE\n");
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mode = "usb";
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env_set("modeboot", "usb_dfu_spl");
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break;
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case JTAG_MODE:
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puts("JTAG_MODE\n");
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mode = "pxe dhcp";
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env_set("modeboot", "jtagboot");
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break;
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case QSPI_MODE_24BIT:
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case QSPI_MODE_32BIT:
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mode = "qspi0";
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puts("QSPI_MODE\n");
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env_set("modeboot", "qspiboot");
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break;
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case EMMC_MODE:
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puts("EMMC_MODE\n");
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mode = "mmc0";
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env_set("modeboot", "emmcboot");
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break;
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case SD_MODE:
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puts("SD_MODE\n");
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mode = "mmc0";
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env_set("modeboot", "sdboot");
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break;
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case SD1_LSHFT_MODE:
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puts("LVL_SHFT_");
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/* fall through */
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case SD_MODE1:
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puts("SD_MODE1\n");
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#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
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mode = "mmc1";
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env_set("sdbootdev", "1");
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#else
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mode = "mmc0";
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#endif
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env_set("modeboot", "sdboot");
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break;
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case NAND_MODE:
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puts("NAND_MODE\n");
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mode = "nand0";
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env_set("modeboot", "nandboot");
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break;
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default:
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mode = "";
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printf("Invalid Boot Mode:0x%x\n", bootmode);
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break;
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}
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/*
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* One terminating char + one byte for space between mode
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* and default boot_targets
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*/
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new_targets = calloc(1, strlen(mode) +
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strlen(env_get("boot_targets")) + 2);
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sprintf(new_targets, "%s %s", mode, env_get("boot_targets"));
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env_set("boot_targets", new_targets);
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: Xilinx ZynqMP\n");
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return 0;
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}
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#ifdef CONFIG_USB_DWC3
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static struct dwc3_device dwc3_device_data0 = {
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.maximum_speed = USB_SPEED_HIGH,
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.base = ZYNQMP_USB0_XHCI_BASEADDR,
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.dr_mode = USB_DR_MODE_PERIPHERAL,
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.index = 0,
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};
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static struct dwc3_device dwc3_device_data1 = {
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.maximum_speed = USB_SPEED_HIGH,
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.base = ZYNQMP_USB1_XHCI_BASEADDR,
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.dr_mode = USB_DR_MODE_PERIPHERAL,
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.index = 1,
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};
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int usb_gadget_handle_interrupts(int index)
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{
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dwc3_uboot_handle_interrupt(index);
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return 0;
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}
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int board_usb_init(int index, enum usb_init_type init)
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{
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debug("%s: index %x\n", __func__, index);
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#if defined(CONFIG_USB_GADGET_DOWNLOAD)
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g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
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#endif
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switch (index) {
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case 0:
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return dwc3_uboot_init(&dwc3_device_data0);
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case 1:
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return dwc3_uboot_init(&dwc3_device_data1);
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};
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return -1;
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}
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int board_usb_cleanup(int index, enum usb_init_type init)
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{
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dwc3_uboot_exit(index);
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return 0;
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}
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#endif
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