Dave Liu ec145e87b8 fsl-ddr: Fix the turnaround timing for TIMING_CFG_4 ... Read-to-read/Write-to-write turnaround for same chip select of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and OTF case, BL/2 cycles is enough for fixed BL8. Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2 will improve the memory performance. Signed-off-by: Dave Liu <daveliu@freescale.com>		2010-04-07 00:07:23 -05:00
..
ddr	fsl-ddr: Fix the turnaround timing for TIMING_CFG_4	2010-04-07 00:07:23 -05:00
cpu.c	ppc/p4080: Add various p4080 related defines (and p4040)	2009-09-24 12:05:28 -05:00
fdt.c	ppc/85xx/86xx: Device tree fixup for number of cores	2009-09-08 09:10:08 -05:00
Makefile	ppc/85xx/86xx: Device tree fixup for number of cores	2009-09-08 09:10:08 -05:00
pci_cfg.c	ppc/8xxx: Remove is_fsl_pci_agent	2010-01-05 13:49:07 -06:00