mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 03:06:16 +09:00
1fb065feae
Add fine-tuning for the DRAM configuration according to the DRAM chip datasheet. THis configuration applies to both Hynix HY5DU12622DTP and Samsung K5H511538J-D43 . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
111 lines
2.3 KiB
C
111 lines
2.3 KiB
C
/*
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* Olimex MX23 Olinuxino board
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*
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* Copyright (C) 2013 Marek Vasut <marex@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/iomux-mx23.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#ifdef CONFIG_STATUS_LED
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#include <status_led.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Functions
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*/
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int board_early_init_f(void)
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{
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/* IO0 clock at 480MHz */
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mxs_set_ioclk(MXC_IOCLK0, 480000);
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/* SSP0 clock at 96MHz */
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mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
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return 0;
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}
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#ifdef CONFIG_CMD_USB
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int board_ehci_hcd_init(int port)
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{
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/* Enable LAN9512 (Maxi) or GL850G (Mini) USB HUB power. */
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gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 1);
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udelay(100);
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return 0;
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}
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int board_ehci_hcd_exit(int port)
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{
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/* Enable LAN9512 (Maxi) or GL850G (Mini) USB HUB power. */
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gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 0);
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return 0;
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}
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#endif
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int dram_init(void)
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{
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return mxs_dram_init();
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}
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#ifdef CONFIG_CMD_MMC
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static int mx23_olx_mmc_cd(int id)
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{
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return 1; /* Card always present */
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}
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int board_mmc_init(bd_t *bis)
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{
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return mxsmmc_initialize(bis, 0, NULL, mx23_olx_mmc_cd);
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}
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#endif
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int board_init(void)
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{
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/* Adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
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status_led_set(STATUS_LED_BOOT, STATUS_LED_STATE);
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#endif
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return 0;
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}
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/* Fine-tune the DRAM configuration. */
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void mxs_adjust_memory_params(uint32_t *dram_vals)
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{
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/* Enable Auto Precharge. */
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dram_vals[3] |= 1 << 8;
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/* Enable Fast Writes. */
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dram_vals[5] |= 1 << 8;
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/* tEMRS = 3*tCK */
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dram_vals[10] &= ~(0x3 << 8);
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dram_vals[10] |= (0x3 << 8);
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/* CASLAT = 3*tCK */
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dram_vals[11] &= ~(0x3 << 0);
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dram_vals[11] |= (0x3 << 0);
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/* tCKE = 1*tCK */
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dram_vals[12] &= ~(0x7 << 0);
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dram_vals[12] |= (0x1 << 0);
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/* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */
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dram_vals[13] &= ~((0xf << 16) | (0xf << 24) | (0xf << 0));
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dram_vals[13] |= (0x6 << 16) | (0x6 << 24) | (0x2 << 0);
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/* tDAL = 6*tCK */
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dram_vals[15] &= ~(0xf << 16);
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dram_vals[15] |= (0x6 << 16);
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/* tREF = 1040*tCK */
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dram_vals[26] &= ~0xffff;
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dram_vals[26] |= 0x0410;
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/* tRAS_MAX = 9334*tCK */
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dram_vals[32] &= ~0xffff;
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dram_vals[32] |= 0x2475;
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}
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