mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-05 01:33:44 +09:00
85b8c5c4bf
Conflicts: arch/arm/cpu/arm926ejs/mxs/Makefile board/compulab/cm_t35/Makefile board/corscience/tricorder/Makefile board/ppcag/bg0900/Makefile drivers/bootcount/Makefile include/configs/omap4_common.h include/configs/pdnb3.h Makefile conflicts are due to additions/removals of object files on the ARM branch vs KBuild introduction on the main branch. Resolution consists in adjusting the list of object files in the main branch version. This also applies to two files which are not listed as conflicting but had to be modified: board/compulab/common/Makefile board/udoo/Makefile include/configs/omap4_common.h conflicts are due to the OMAP4 conversion to ti_armv7_common.h on the ARM side, and CONFIG_SYS_HZ removal on the main side. Resolution is to convert as this icludes removal of CONFIG_SYS_HZ. include/configs/pdnb3.h is due to a removal on ARM side. Trivial resolution is to remove the file. Note: 'git show' will also list two files just because they are new: include/configs/am335x_igep0033.h include/configs/omap3_igep00x0.h
603 lines
20 KiB
C
603 lines
20 KiB
C
/*
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* (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il>
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*
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* Authors: Mike Rapoport <mike@compulab.co.il>
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* Igor Grinberg <grinberg@compulab.co.il>
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*
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* Derived from omap3evm and Beagle Board by
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* Manikandan Pillai <mani.pillai@ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <x0khasim@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <status_led.h>
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#include <netdev.h>
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#include <net.h>
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#include <i2c.h>
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#include <usb.h>
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#include <mmc.h>
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#include <nand.h>
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#include <twl4030.h>
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#include <bmp_layout.h>
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#include <linux/compiler.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-types.h>
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#include <asm/ehci-omap.h>
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#include <asm/gpio.h>
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#include "../common/eeprom.h"
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DECLARE_GLOBAL_DATA_PTR;
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const omap3_sysinfo sysinfo = {
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DDR_DISCRETE,
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"CM-T3x board",
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"NAND",
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};
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static u32 gpmc_net_config[GPMC_MAX_REG] = {
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NET_GPMC_CONFIG1,
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NET_GPMC_CONFIG2,
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NET_GPMC_CONFIG3,
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NET_GPMC_CONFIG4,
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NET_GPMC_CONFIG5,
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NET_GPMC_CONFIG6,
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0
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};
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static u32 gpmc_nand_config[GPMC_MAX_REG] = {
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SMNAND_GPMC_CONFIG1,
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SMNAND_GPMC_CONFIG2,
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SMNAND_GPMC_CONFIG3,
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SMNAND_GPMC_CONFIG4,
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SMNAND_GPMC_CONFIG5,
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SMNAND_GPMC_CONFIG6,
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0,
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};
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#ifdef CONFIG_LCD
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#ifdef CONFIG_CMD_NAND
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static int splash_load_from_nand(u32 bmp_load_addr)
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{
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struct bmp_header *bmp_hdr;
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int res, splash_screen_nand_offset = 0x100000;
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size_t bmp_size, bmp_header_size = sizeof(struct bmp_header);
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if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp)
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goto splash_address_too_high;
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res = nand_read_skip_bad(&nand_info[nand_curr_device],
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splash_screen_nand_offset, &bmp_header_size,
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NULL, nand_info[nand_curr_device].size,
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(u_char *)bmp_load_addr);
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if (res < 0)
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return res;
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bmp_hdr = (struct bmp_header *)bmp_load_addr;
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bmp_size = le32_to_cpu(bmp_hdr->file_size);
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if (bmp_load_addr + bmp_size >= gd->start_addr_sp)
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goto splash_address_too_high;
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return nand_read_skip_bad(&nand_info[nand_curr_device],
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splash_screen_nand_offset, &bmp_size,
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NULL, nand_info[nand_curr_device].size,
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(u_char *)bmp_load_addr);
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splash_address_too_high:
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printf("Error: splashimage address too high. Data overwrites U-Boot "
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"and/or placed beyond DRAM boundaries.\n");
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return -1;
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}
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#else
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static inline int splash_load_from_nand(void)
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{
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return -1;
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}
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#endif /* CONFIG_CMD_NAND */
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int splash_screen_prepare(void)
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{
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char *env_splashimage_value;
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u32 bmp_load_addr;
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env_splashimage_value = getenv("splashimage");
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if (env_splashimage_value == NULL)
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return -1;
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bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16);
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if (bmp_load_addr == 0) {
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printf("Error: bad splashimage address specified\n");
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return -1;
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}
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return splash_load_from_nand(bmp_load_addr);
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}
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#endif /* CONFIG_LCD */
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/*
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* Routine: board_init
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* Description: hardware init.
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*/
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int board_init(void)
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{
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0],
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CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M);
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/* board id for Linux */
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if (get_cpu_family() == CPU_OMAP34XX)
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gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
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else
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gd->bd->bi_arch_number = MACH_TYPE_CM_T3730;
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
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status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
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#endif
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return 0;
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}
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static u32 cm_t3x_rev;
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/*
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* Routine: get_board_rev
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* Description: read system revision
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*/
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u32 get_board_rev(void)
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{
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if (!cm_t3x_rev)
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cm_t3x_rev = cl_eeprom_get_board_rev();
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return cm_t3x_rev;
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};
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/*
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* Routine: misc_init_r
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* Description: display die ID
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*/
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int misc_init_r(void)
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{
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u32 board_rev = get_board_rev();
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u32 rev_major = board_rev / 100;
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u32 rev_minor = board_rev - (rev_major * 100);
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if ((rev_minor / 10) * 10 == rev_minor)
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rev_minor = rev_minor / 10;
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printf("PCB: %u.%u\n", rev_major, rev_minor);
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dieid_num_r();
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return 0;
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}
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/*
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers specific to the
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* hardware. Many pins need to be moved from protect to primary
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* mode.
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*/
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static void cm_t3x_set_common_muxconf(void)
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{
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/* SDRC */
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MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/
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MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/
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MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/
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MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/
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MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/
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MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/
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MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/
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MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/
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MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/
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MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/
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MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/
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MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/
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MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/
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MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/
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MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/
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MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/
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MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/
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MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/
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MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/
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MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/
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MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/
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MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/
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MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/
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MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/
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MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/
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MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/
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MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/
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MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/
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MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/
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MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/
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MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/
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MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/
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MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/
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MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/
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MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/
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MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/
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MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/
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MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/
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MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/
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/* GPMC */
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MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/
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MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/
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MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/
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MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/
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MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/
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MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/
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MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/
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MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/
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MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/
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MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/
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MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/
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MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/
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MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/
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MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/
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MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/
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MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/
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MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/
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MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/
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MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/
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MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/
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MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/
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MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/
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MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/
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MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/
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MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/
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MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/
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MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/
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/* SB-T35 Ethernet */
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MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/
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/* DVI enable */
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MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/
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/* CM-T3x Ethernet */
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MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/
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MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/
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MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*nADV_ALE*/
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MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*nOE*/
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MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*nWE*/
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MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*nBE0_CLE*/
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MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); /*GPIO_61*/
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MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*nWP*/
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MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*WAIT0*/
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/* DSS */
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MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/
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MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/
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MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/
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MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/
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MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/
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MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/
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MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/
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MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/
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MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/
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MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/
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MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/
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MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/
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MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/
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MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/
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MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/
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MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/
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/* serial interface */
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MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX*/
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MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX*/
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/* mUSB */
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MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/
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MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/
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MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/
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MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/
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MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/
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MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/
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MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/
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MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/
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MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/
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MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/
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MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/
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MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/
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/* USB EHCI */
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MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/
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MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/
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MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/
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MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/
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MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/
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MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/
|
|
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/
|
|
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/
|
|
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/
|
|
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/
|
|
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/
|
|
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/
|
|
|
|
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/
|
|
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/
|
|
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/
|
|
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/
|
|
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/
|
|
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/
|
|
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/
|
|
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/
|
|
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/
|
|
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/
|
|
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/
|
|
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
|
|
|
|
/* SB_T35_USB_HUB_RESET_GPIO */
|
|
MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)); /*GPIO_167*/
|
|
|
|
/* I2C1 */
|
|
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/
|
|
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/
|
|
/* I2C2 */
|
|
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/
|
|
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/
|
|
/* I2C3 */
|
|
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/
|
|
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/
|
|
|
|
/* control and debug */
|
|
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/
|
|
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/
|
|
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/
|
|
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/
|
|
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/
|
|
MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/
|
|
MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); /*JTAG_nTRST*/
|
|
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/
|
|
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/
|
|
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/
|
|
|
|
/* MMC1 */
|
|
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/
|
|
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/
|
|
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/
|
|
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/
|
|
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/
|
|
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/
|
|
}
|
|
|
|
static void cm_t35_set_muxconf(void)
|
|
{
|
|
/* DSS */
|
|
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/
|
|
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/
|
|
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/
|
|
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/
|
|
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/
|
|
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/
|
|
|
|
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/
|
|
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/
|
|
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/
|
|
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/
|
|
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/
|
|
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/
|
|
|
|
/* MMC1 */
|
|
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/
|
|
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/
|
|
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/
|
|
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/
|
|
}
|
|
|
|
static void cm_t3730_set_muxconf(void)
|
|
{
|
|
/* DSS */
|
|
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)); /*DSS_DATA0*/
|
|
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)); /*DSS_DATA1*/
|
|
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)); /*DSS_DATA2*/
|
|
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)); /*DSS_DATA3*/
|
|
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)); /*DSS_DATA4*/
|
|
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)); /*DSS_DATA5*/
|
|
|
|
MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)); /*DSS_DATA18*/
|
|
MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)); /*DSS_DATA19*/
|
|
MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)); /*DSS_DATA20*/
|
|
MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)); /*DSS_DATA21*/
|
|
MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)); /*DSS_DATA22*/
|
|
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)); /*DSS_DATA23*/
|
|
}
|
|
|
|
void set_muxconf_regs(void)
|
|
{
|
|
cm_t3x_set_common_muxconf();
|
|
|
|
if (get_cpu_family() == CPU_OMAP34XX)
|
|
cm_t35_set_muxconf();
|
|
else
|
|
cm_t3730_set_muxconf();
|
|
}
|
|
|
|
#ifdef CONFIG_GENERIC_MMC
|
|
int board_mmc_getcd(struct mmc *mmc)
|
|
{
|
|
u8 val;
|
|
|
|
if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO, &val))
|
|
return -1;
|
|
|
|
return !(val & 1);
|
|
}
|
|
|
|
int board_mmc_init(bd_t *bis)
|
|
{
|
|
return omap_mmc_init(0, 0, 0, -1, 59);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Routine: setup_net_chip_gmpc
|
|
* Description: Setting up the configuration GPMC registers specific to the
|
|
* Ethernet hardware.
|
|
*/
|
|
static void setup_net_chip_gmpc(void)
|
|
{
|
|
struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
|
|
|
|
enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5],
|
|
CM_T3X_SMC911X_BASE, GPMC_SIZE_16M);
|
|
enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4],
|
|
SB_T35_SMC911X_BASE, GPMC_SIZE_16M);
|
|
|
|
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
|
|
writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
|
|
|
|
/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
|
|
writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
|
|
|
|
/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
|
|
writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
|
|
&ctrl_base->gpmc_nadv_ale);
|
|
}
|
|
|
|
#ifdef CONFIG_DRIVER_OMAP34XX_I2C
|
|
/*
|
|
* Routine: reset_net_chip
|
|
* Description: reset the Ethernet controller via TPS65930 GPIO
|
|
*/
|
|
static void reset_net_chip(void)
|
|
{
|
|
/* Set GPIO1 of TPS65930 as output */
|
|
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03,
|
|
0x02);
|
|
/* Send a pulse on the GPIO pin */
|
|
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C,
|
|
0x02);
|
|
udelay(1);
|
|
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x09,
|
|
0x02);
|
|
mdelay(40);
|
|
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C,
|
|
0x02);
|
|
mdelay(1);
|
|
}
|
|
#else
|
|
static inline void reset_net_chip(void) {}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SMC911X
|
|
/*
|
|
* Routine: handle_mac_address
|
|
* Description: prepare MAC address for on-board Ethernet.
|
|
*/
|
|
static int handle_mac_address(void)
|
|
{
|
|
unsigned char enetaddr[6];
|
|
int rc;
|
|
|
|
rc = eth_getenv_enetaddr("ethaddr", enetaddr);
|
|
if (rc)
|
|
return 0;
|
|
|
|
rc = cl_eeprom_read_mac_addr(enetaddr);
|
|
if (rc)
|
|
return rc;
|
|
|
|
if (!is_valid_ether_addr(enetaddr))
|
|
return -1;
|
|
|
|
return eth_setenv_enetaddr("ethaddr", enetaddr);
|
|
}
|
|
|
|
|
|
/*
|
|
* Routine: board_eth_init
|
|
* Description: initialize module and base-board Ethernet chips
|
|
*/
|
|
int board_eth_init(bd_t *bis)
|
|
{
|
|
int rc = 0, rc1 = 0;
|
|
|
|
setup_net_chip_gmpc();
|
|
reset_net_chip();
|
|
|
|
rc1 = handle_mac_address();
|
|
if (rc1)
|
|
printf("No MAC address found! ");
|
|
|
|
rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE);
|
|
if (rc1 > 0)
|
|
rc++;
|
|
|
|
rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE);
|
|
if (rc1 > 0)
|
|
rc++;
|
|
|
|
return rc;
|
|
}
|
|
#endif
|
|
|
|
void __weak get_board_serial(struct tag_serialnr *serialnr)
|
|
{
|
|
/*
|
|
* This corresponds to what happens when we can communicate with the
|
|
* eeprom but don't get a valid board serial value.
|
|
*/
|
|
serialnr->low = 0;
|
|
serialnr->high = 0;
|
|
};
|
|
|
|
#ifdef CONFIG_USB_EHCI_OMAP
|
|
struct omap_usbhs_board_data usbhs_bdata = {
|
|
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
|
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
|
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
|
};
|
|
|
|
#define SB_T35_USB_HUB_RESET_GPIO 167
|
|
int ehci_hcd_init(int index, enum usb_init_type init,
|
|
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
|
|
{
|
|
u8 val;
|
|
int offset;
|
|
|
|
if (gpio_request(SB_T35_USB_HUB_RESET_GPIO, "SB-T35 usb hub reset")) {
|
|
printf("Error: can't obtain GPIO %d for SB-T35 usb hub reset",
|
|
SB_T35_USB_HUB_RESET_GPIO);
|
|
return -1;
|
|
}
|
|
|
|
gpio_direction_output(SB_T35_USB_HUB_RESET_GPIO, 0);
|
|
udelay(10);
|
|
gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1);
|
|
udelay(1000);
|
|
|
|
offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1;
|
|
twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val);
|
|
/* Set GPIO6 and GPIO7 of TPS65930 as output */
|
|
val |= 0xC0;
|
|
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, val);
|
|
offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1;
|
|
/* Take both PHYs out of reset */
|
|
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, 0xC0);
|
|
udelay(1);
|
|
|
|
return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
|
|
}
|
|
|
|
int ehci_hcd_stop(void)
|
|
{
|
|
return omap_ehci_hcd_stop();
|
|
}
|
|
#endif /* CONFIG_USB_EHCI_OMAP */
|