mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-23 11:29:43 +09:00
eb53941206
Boot space translation utilizes the pre-translation address to select the DDR controller target. However, the post-translation address will be presented to the selected DDR controller. It is possible that the pre- translation address selects one DDR controller but the post-translation address exists in a different DDR controller when using certain DDR controller interleaving modes. The device may fail to boot under these circumstances. Note that a DDR MSE error will not be detected since DDR controller bounds registers are programmed to be the same when configured for DDR controller interleaving. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
||
|---|---|---|
| .. | ||
| cache.S | ||
| config.mk | ||
| cpu_init.c | ||
| cpu.c | ||
| ddr-8641.c | ||
| fdt.c | ||
| interrupts.c | ||
| Makefile | ||
| mp.c | ||
| mpc8610_serdes.c | ||
| mpc8641_serdes.c | ||
| release.S | ||
| speed.c | ||
| start.S | ||
| traps.c | ||
| u-boot.lds | ||