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https://github.com/brain-hackers/u-boot-brain
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fdc7718999
Add the dts files to support deivce tree, update the configuration files to support the device tree and driver model. The peripheral clock and pins configuration are handled by the clock and the pinctrl drivers respectively. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
127 lines
3.0 KiB
C
127 lines
3.0 KiB
C
/*
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* (C) Copyright 2007-2013
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* Stelian Pop <stelian.pop@leadtechdesign.com>
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* Lead Tech Design <www.leadtechdesign.com>
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* Thomas Petazzoni, Free Electrons, <thomas.petazzoni@free-electrons.com>
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* Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_matrix.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm-generic/gpio.h>
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#include <asm/io.h>
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#include <net.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_CMD_NAND
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static void usb_a9263_nand_hw_init(void)
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{
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unsigned long csa;
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at91_smc_t *smc = (at91_smc_t *)ATMEL_BASE_SMC0;
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at91_matrix_t *matrix = (at91_matrix_t *)ATMEL_BASE_MATRIX;
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/* Enable CS3 */
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csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
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writel(csa, &matrix->csa[0]);
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/* Configure SMC CS3 for NAND/SmartMedia */
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
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&smc->cs[3].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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AT91_SMC_MODE_DBW_8 |
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AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode);
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at91_periph_clk_enable(ATMEL_ID_PIOA);
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at91_periph_clk_enable(ATMEL_ID_PIOCDE);
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/* Configure RDY/BSY */
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gpio_request(CONFIG_SYS_NAND_READY_PIN, "NAND ready/busy");
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gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
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/* Enable NandFlash */
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gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "NAND enable");
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gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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}
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#endif
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#ifdef CONFIG_MACB
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static void usb_a9263_macb_hw_init(void)
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{
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at91_periph_clk_enable(ATMEL_ID_EMAC);
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/*
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* Disable pull-up on:
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* RXDV (PC25) => PHY normal mode (not Test mode)
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* ERX0 (PE25) => PHY ADDR0
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* ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
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*
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* PHY has internal weak pull-up/pull-down
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*/
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gpio_request(GPIO_PIN_PC(25), "PHY mode");
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gpio_direction_input(GPIO_PIN_PC(25));
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gpio_request(GPIO_PIN_PE(25), "PHY ADDR0");
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gpio_direction_input(GPIO_PIN_PE(25));
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gpio_request(GPIO_PIN_PE(26), "PHY ADDR1");
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gpio_direction_input(GPIO_PIN_PE(26));
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at91_phy_reset();
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/* It will set proper pinmux for ports PC25, PE25-26 */
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at91_macb_hw_init();
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}
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#endif
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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#ifdef CONFIG_CMD_NAND
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usb_a9263_nand_hw_init();
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#endif
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#ifdef CONFIG_MACB
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usb_a9263_macb_hw_init();
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#endif
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#ifdef CONFIG_USB_OHCI_NEW
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at91_uhp_hw_init();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_MACB
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rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x0001);
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#endif
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return rc;
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}
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