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https://github.com/brain-hackers/u-boot-brain
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LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
10 lines
274 B
Makefile
10 lines
274 B
Makefile
# SPDX-License-Identifier: GPL-2.0+
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# Copyright 2015-2018 NXP
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# Copyright 2014 Freescale Semiconductor, Inc.
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obj-y += ldpaa_wriop.o
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obj-y += ldpaa_eth.o
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obj-$(CONFIG_ARCH_LS2080A) += ls2080a.o
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obj-$(CONFIG_ARCH_LS1088A) += ls1088a.o
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obj-$(CONFIG_ARCH_LX2160A) += lx2160a.o
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