mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
617 lines
22 KiB
C
617 lines
22 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*------------------------------------------------------------------------
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* lan91c96.h
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Rolf Offermanns <rof@sysgo.de>
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* Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
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* Developed by Simple Network Magic Corporation (SNMC)
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* Copyright (C) 1996 by Erik Stahlman (ES)
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*
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* This file contains register information and access macros for
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* the LAN91C96 single chip ethernet controller. It is a modified
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* version of the smc9111.h file.
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*
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* Information contained in this file was obtained from the LAN91C96
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* manual from SMC. To get a copy, if you really want one, you can find
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* information under www.smsc.com.
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*
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* Authors
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* Erik Stahlman ( erik@vt.edu )
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* Daris A Nevil ( dnevil@snmc.com )
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*
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* History
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* 04/30/03 Mathijs Haarman Modified smc91111.h (u-boot version)
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* for lan91c96
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*-------------------------------------------------------------------------
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*/
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#ifndef _LAN91C96_H_
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#define _LAN91C96_H_
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#include <asm/types.h>
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#include <asm/io.h>
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#include <config.h>
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/* I want some simple types */
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typedef unsigned char byte;
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typedef unsigned short word;
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typedef unsigned long int dword;
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/*
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* DEBUGGING LEVELS
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*
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* 0 for normal operation
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* 1 for slightly more details
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* >2 for various levels of increasingly useless information
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* 2 for interrupt tracking, status flags
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* 3 for packet info
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* 4 for complete packet dumps
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*/
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/*#define SMC_DEBUG 0 */
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/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */
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#define SMC_IO_EXTENT 16
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#ifdef CONFIG_CPU_PXA25X
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#define SMC_IO_SHIFT 0
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#define SMCREG(edev, r) ((edev)->iobase+((r)<<SMC_IO_SHIFT))
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#define SMC_inl(edev, r) (*((volatile dword *)SMCREG(edev, r)))
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#define SMC_inw(edev, r) (*((volatile word *)SMCREG(edev, r)))
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#define SMC_inb(edev, p) ({ \
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unsigned int __p = p; \
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unsigned int __v = SMC_inw(edev, __p & ~1); \
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if (__p & 1) __v >>= 8; \
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else __v &= 0xff; \
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__v; })
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#define SMC_outl(edev, d, r) (*((volatile dword *)SMCREG(edev, r)) = d)
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#define SMC_outw(edev, d, r) (*((volatile word *)SMCREG(edev, r)) = d)
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#define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \
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word __w = SMC_inw(edev, (r)&~1); \
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__w &= ((r)&1) ? 0x00FF : 0xFF00; \
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__w |= ((r)&1) ? __d<<8 : __d; \
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SMC_outw(edev, __w, (r)&~1); \
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})
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#define SMC_outsl(edev, r, b, l) ({ int __i; \
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dword *__b2; \
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__b2 = (dword *) b; \
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for (__i = 0; __i < l; __i++) { \
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SMC_outl(edev, *(__b2 + __i),\
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r); \
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} \
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})
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#define SMC_outsw(edev, r, b, l) ({ int __i; \
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word *__b2; \
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__b2 = (word *) b; \
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for (__i = 0; __i < l; __i++) { \
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SMC_outw(edev, *(__b2 + __i),\
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r); \
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} \
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})
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#define SMC_insl(edev, r, b, l) ({ int __i ; \
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dword *__b2; \
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__b2 = (dword *) b; \
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for (__i = 0; __i < l; __i++) { \
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*(__b2 + __i) = SMC_inl(edev,\
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r); \
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SMC_inl(edev, 0); \
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}; \
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})
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#define SMC_insw(edev, r, b, l) ({ int __i ; \
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word *__b2; \
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__b2 = (word *) b; \
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for (__i = 0; __i < l; __i++) { \
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*(__b2 + __i) = SMC_inw(edev,\
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r); \
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SMC_inw(edev, 0); \
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}; \
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})
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#define SMC_insb(edev, r, b, l) ({ int __i ; \
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byte *__b2; \
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__b2 = (byte *) b; \
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for (__i = 0; __i < l; __i++) { \
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*(__b2 + __i) = SMC_inb(edev,\
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r); \
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SMC_inb(edev, 0); \
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}; \
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})
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#else /* if not CONFIG_CPU_PXA25X */
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/*
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* We have only 16 Bit PCMCIA access on Socket 0
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*/
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#define SMC_inw(edev, r) (*((volatile word *)((edev)->iobase+(r))))
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#define SMC_inb(edev, r) (((r)&1) ? SMC_inw(edev, (r)&~1)>>8 :\
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SMC_inw(edev, r)&0xFF)
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#define SMC_outw(edev, d, r) (*((volatile word *)((edev)->iobase+(r))) = d)
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#define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \
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word __w = SMC_inw(edev, (r)&~1); \
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__w &= ((r)&1) ? 0x00FF : 0xFF00; \
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__w |= ((r)&1) ? __d<<8 : __d; \
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SMC_outw(edev, __w, (r)&~1); \
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})
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#define SMC_outsw(edev, r, b, l) ({ int __i; \
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word *__b2; \
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__b2 = (word *) b; \
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for (__i = 0; __i < l; __i++) { \
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SMC_outw(edev, *(__b2 + __i),\
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r); \
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} \
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})
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#define SMC_insw(edev, r, b, l) ({ int __i ; \
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word *__b2; \
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__b2 = (word *) b; \
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for (__i = 0; __i < l; __i++) { \
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*(__b2 + __i) = SMC_inw(edev,\
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r); \
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SMC_inw(edev, 0); \
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}; \
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})
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#endif
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/*
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****************************************************************************
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* Bank Select Field
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****************************************************************************
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*/
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#define LAN91C96_BANK_SELECT 14 /* Bank Select Register */
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#define LAN91C96_BANKSELECT (0x3UC << 0)
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#define BANK0 0x00
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#define BANK1 0x01
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#define BANK2 0x02
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#define BANK3 0x03
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#define BANK4 0x04
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/*
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****************************************************************************
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* EEPROM Addresses.
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****************************************************************************
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*/
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#define EEPROM_MAC_OFFSET_1 0x6020
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#define EEPROM_MAC_OFFSET_2 0x6021
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#define EEPROM_MAC_OFFSET_3 0x6022
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/*
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****************************************************************************
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* Bank 0 Register Map in I/O Space
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****************************************************************************
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*/
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#define LAN91C96_TCR 0 /* Transmit Control Register */
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#define LAN91C96_EPH_STATUS 2 /* EPH Status Register */
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#define LAN91C96_RCR 4 /* Receive Control Register */
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#define LAN91C96_COUNTER 6 /* Counter Register */
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#define LAN91C96_MIR 8 /* Memory Information Register */
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#define LAN91C96_MCR 10 /* Memory Configuration Register */
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/*
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****************************************************************************
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* Transmit Control Register - Bank 0 - Offset 0
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****************************************************************************
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*/
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#define LAN91C96_TCR_TXENA (0x1U << 0)
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#define LAN91C96_TCR_LOOP (0x1U << 1)
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#define LAN91C96_TCR_FORCOL (0x1U << 2)
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#define LAN91C96_TCR_TXP_EN (0x1U << 3)
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#define LAN91C96_TCR_PAD_EN (0x1U << 7)
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#define LAN91C96_TCR_NOCRC (0x1U << 8)
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#define LAN91C96_TCR_MON_CSN (0x1U << 10)
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#define LAN91C96_TCR_FDUPLX (0x1U << 11)
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#define LAN91C96_TCR_STP_SQET (0x1U << 12)
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#define LAN91C96_TCR_EPH_LOOP (0x1U << 13)
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#define LAN91C96_TCR_ETEN_TYPE (0x1U << 14)
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#define LAN91C96_TCR_FDSE (0x1U << 15)
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/*
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****************************************************************************
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* EPH Status Register - Bank 0 - Offset 2
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****************************************************************************
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*/
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#define LAN91C96_EPHSR_TX_SUC (0x1U << 0)
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#define LAN91C96_EPHSR_SNGL_COL (0x1U << 1)
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#define LAN91C96_EPHSR_MUL_COL (0x1U << 2)
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#define LAN91C96_EPHSR_LTX_MULT (0x1U << 3)
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#define LAN91C96_EPHSR_16COL (0x1U << 4)
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#define LAN91C96_EPHSR_SQET (0x1U << 5)
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#define LAN91C96_EPHSR_LTX_BRD (0x1U << 6)
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#define LAN91C96_EPHSR_TX_DEFR (0x1U << 7)
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#define LAN91C96_EPHSR_WAKEUP (0x1U << 8)
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#define LAN91C96_EPHSR_LATCOL (0x1U << 9)
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#define LAN91C96_EPHSR_LOST_CARR (0x1U << 10)
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#define LAN91C96_EPHSR_EXC_DEF (0x1U << 11)
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#define LAN91C96_EPHSR_CTR_ROL (0x1U << 12)
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#define LAN91C96_EPHSR_LINK_OK (0x1U << 14)
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#define LAN91C96_EPHSR_TX_UNRN (0x1U << 15)
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#define LAN91C96_EPHSR_ERRORS (LAN91C96_EPHSR_SNGL_COL | \
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LAN91C96_EPHSR_MUL_COL | \
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LAN91C96_EPHSR_16COL | \
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LAN91C96_EPHSR_SQET | \
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LAN91C96_EPHSR_TX_DEFR | \
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LAN91C96_EPHSR_LATCOL | \
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LAN91C96_EPHSR_LOST_CARR | \
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LAN91C96_EPHSR_EXC_DEF | \
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LAN91C96_EPHSR_LINK_OK | \
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LAN91C96_EPHSR_TX_UNRN)
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/*
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****************************************************************************
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* Receive Control Register - Bank 0 - Offset 4
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****************************************************************************
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*/
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#define LAN91C96_RCR_RX_ABORT (0x1U << 0)
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#define LAN91C96_RCR_PRMS (0x1U << 1)
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#define LAN91C96_RCR_ALMUL (0x1U << 2)
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#define LAN91C96_RCR_RXEN (0x1U << 8)
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#define LAN91C96_RCR_STRIP_CRC (0x1U << 9)
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#define LAN91C96_RCR_FILT_CAR (0x1U << 14)
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#define LAN91C96_RCR_SOFT_RST (0x1U << 15)
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/*
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****************************************************************************
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* Counter Register - Bank 0 - Offset 6
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****************************************************************************
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*/
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#define LAN91C96_ECR_SNGL_COL (0xFU << 0)
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#define LAN91C96_ECR_MULT_COL (0xFU << 5)
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#define LAN91C96_ECR_DEF_TX (0xFU << 8)
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#define LAN91C96_ECR_EXC_DEF_TX (0xFU << 12)
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/*
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****************************************************************************
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* Memory Information Register - Bank 0 - OFfset 8
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****************************************************************************
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*/
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#define LAN91C96_MIR_SIZE (0x18 << 0) /* 6144 bytes */
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/*
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****************************************************************************
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* Memory Configuration Register - Bank 0 - Offset 10
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****************************************************************************
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*/
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#define LAN91C96_MCR_MEM_RES (0xFFU << 0)
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#define LAN91C96_MCR_MEM_MULT (0x3U << 9)
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#define LAN91C96_MCR_HIGH_ID (0x3U << 12)
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#define LAN91C96_MCR_TRANSMIT_PAGES 0x6
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/*
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****************************************************************************
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* Bank 1 Register Map in I/O Space
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****************************************************************************
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*/
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#define LAN91C96_CONFIG 0 /* Configuration Register */
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#define LAN91C96_BASE 2 /* Base Address Register */
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#define LAN91C96_IA0 4 /* Individual Address Register - 0 */
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#define LAN91C96_IA1 5 /* Individual Address Register - 1 */
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#define LAN91C96_IA2 6 /* Individual Address Register - 2 */
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#define LAN91C96_IA3 7 /* Individual Address Register - 3 */
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#define LAN91C96_IA4 8 /* Individual Address Register - 4 */
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#define LAN91C96_IA5 9 /* Individual Address Register - 5 */
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#define LAN91C96_GEN_PURPOSE 10 /* General Address Registers */
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#define LAN91C96_CONTROL 12 /* Control Register */
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/*
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****************************************************************************
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* Configuration Register - Bank 1 - Offset 0
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****************************************************************************
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*/
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#define LAN91C96_CR_INT_SEL0 (0x1U << 1)
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#define LAN91C96_CR_INT_SEL1 (0x1U << 2)
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#define LAN91C96_CR_RES (0x3U << 3)
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#define LAN91C96_CR_DIS_LINK (0x1U << 6)
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#define LAN91C96_CR_16BIT (0x1U << 7)
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#define LAN91C96_CR_AUI_SELECT (0x1U << 8)
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#define LAN91C96_CR_SET_SQLCH (0x1U << 9)
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#define LAN91C96_CR_FULL_STEP (0x1U << 10)
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#define LAN91C96_CR_NO_WAIT (0x1U << 12)
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/*
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****************************************************************************
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* Base Address Register - Bank 1 - Offset 2
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****************************************************************************
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*/
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#define LAN91C96_BAR_RA_BITS (0x27U << 0)
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#define LAN91C96_BAR_ROM_SIZE (0x1U << 6)
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#define LAN91C96_BAR_A_BITS (0xFFU << 8)
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/*
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****************************************************************************
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* Control Register - Bank 1 - Offset 12
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****************************************************************************
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*/
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#define LAN91C96_CTR_STORE (0x1U << 0)
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#define LAN91C96_CTR_RELOAD (0x1U << 1)
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#define LAN91C96_CTR_EEPROM (0x1U << 2)
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#define LAN91C96_CTR_TE_ENABLE (0x1U << 5)
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#define LAN91C96_CTR_CR_ENABLE (0x1U << 6)
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#define LAN91C96_CTR_LE_ENABLE (0x1U << 7)
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#define LAN91C96_CTR_BIT_8 (0x1U << 8)
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#define LAN91C96_CTR_AUTO_RELEASE (0x1U << 11)
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#define LAN91C96_CTR_WAKEUP_EN (0x1U << 12)
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#define LAN91C96_CTR_PWRDN (0x1U << 13)
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#define LAN91C96_CTR_RCV_BAD (0x1U << 14)
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/*
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****************************************************************************
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* Bank 2 Register Map in I/O Space
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****************************************************************************
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*/
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#define LAN91C96_MMU 0 /* MMU Command Register */
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#define LAN91C96_AUTO_TX_START 1 /* Auto Tx Start Register */
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#define LAN91C96_PNR 2 /* Packet Number Register */
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#define LAN91C96_ARR 3 /* Allocation Result Register */
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#define LAN91C96_FIFO 4 /* FIFO Ports Register */
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#define LAN91C96_POINTER 6 /* Pointer Register */
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#define LAN91C96_DATA_HIGH 8 /* Data High Register */
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#define LAN91C96_DATA_LOW 10 /* Data Low Register */
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#define LAN91C96_INT_STATS 12 /* Interrupt Status Register - RO */
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#define LAN91C96_INT_ACK 12 /* Interrupt Acknowledge Register -WO */
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#define LAN91C96_INT_MASK 13 /* Interrupt Mask Register */
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/*
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****************************************************************************
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* MMU Command Register - Bank 2 - Offset 0
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****************************************************************************
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*/
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#define LAN91C96_MMUCR_NO_BUSY (0x1U << 0)
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#define LAN91C96_MMUCR_N1 (0x1U << 1)
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#define LAN91C96_MMUCR_N2 (0x1U << 2)
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#define LAN91C96_MMUCR_COMMAND (0xFU << 4)
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#define LAN91C96_MMUCR_ALLOC_TX (0x2U << 4) /* WXYZ = 0010 */
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#define LAN91C96_MMUCR_RESET_MMU (0x4U << 4) /* WXYZ = 0100 */
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#define LAN91C96_MMUCR_REMOVE_RX (0x6U << 4) /* WXYZ = 0110 */
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#define LAN91C96_MMUCR_REMOVE_TX (0x7U << 4) /* WXYZ = 0111 */
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#define LAN91C96_MMUCR_RELEASE_RX (0x8U << 4) /* WXYZ = 1000 */
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#define LAN91C96_MMUCR_RELEASE_TX (0xAU << 4) /* WXYZ = 1010 */
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#define LAN91C96_MMUCR_ENQUEUE (0xCU << 4) /* WXYZ = 1100 */
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#define LAN91C96_MMUCR_RESET_TX (0xEU << 4) /* WXYZ = 1110 */
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/*
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****************************************************************************
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* Auto Tx Start Register - Bank 2 - Offset 1
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****************************************************************************
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*/
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#define LAN91C96_AUTOTX (0xFFU << 0)
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/*
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****************************************************************************
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* Packet Number Register - Bank 2 - Offset 2
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****************************************************************************
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*/
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#define LAN91C96_PNR_TX (0x1FU << 0)
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/*
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****************************************************************************
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* Allocation Result Register - Bank 2 - Offset 3
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****************************************************************************
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*/
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#define LAN91C96_ARR_ALLOC_PN (0x7FU << 0)
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#define LAN91C96_ARR_FAILED (0x1U << 7)
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/*
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****************************************************************************
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* FIFO Ports Register - Bank 2 - Offset 4
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****************************************************************************
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*/
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#define LAN91C96_FIFO_TX_DONE_PN (0x1FU << 0)
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#define LAN91C96_FIFO_TEMPTY (0x1U << 7)
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#define LAN91C96_FIFO_RX_DONE_PN (0x1FU << 8)
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#define LAN91C96_FIFO_RXEMPTY (0x1U << 15)
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/*
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****************************************************************************
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* Pointer Register - Bank 2 - Offset 6
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****************************************************************************
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*/
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#define LAN91C96_PTR_LOW (0xFFU << 0)
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#define LAN91C96_PTR_HIGH (0x7U << 8)
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#define LAN91C96_PTR_AUTO_TX (0x1U << 11)
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#define LAN91C96_PTR_ETEN (0x1U << 12)
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#define LAN91C96_PTR_READ (0x1U << 13)
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#define LAN91C96_PTR_AUTO_INCR (0x1U << 14)
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#define LAN91C96_PTR_RCV (0x1U << 15)
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#define LAN91C96_PTR_RX_FRAME (LAN91C96_PTR_RCV | \
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LAN91C96_PTR_AUTO_INCR | \
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LAN91C96_PTR_READ)
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/*
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****************************************************************************
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* Data Register - Bank 2 - Offset 8
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****************************************************************************
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*/
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#define LAN91C96_CONTROL_CRC (0x1U << 4) /* CRC bit */
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#define LAN91C96_CONTROL_ODD (0x1U << 5) /* ODD bit */
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/*
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****************************************************************************
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* Interrupt Status Register - Bank 2 - Offset 12
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****************************************************************************
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*/
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#define LAN91C96_IST_RCV_INT (0x1U << 0)
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#define LAN91C96_IST_TX_INT (0x1U << 1)
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#define LAN91C96_IST_TX_EMPTY_INT (0x1U << 2)
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#define LAN91C96_IST_ALLOC_INT (0x1U << 3)
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#define LAN91C96_IST_RX_OVRN_INT (0x1U << 4)
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#define LAN91C96_IST_EPH_INT (0x1U << 5)
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#define LAN91C96_IST_ERCV_INT (0x1U << 6)
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#define LAN91C96_IST_RX_IDLE_INT (0x1U << 7)
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/*
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****************************************************************************
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* Interrupt Acknowledge Register - Bank 2 - Offset 12
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****************************************************************************
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*/
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#define LAN91C96_ACK_TX_INT (0x1U << 1)
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#define LAN91C96_ACK_TX_EMPTY_INT (0x1U << 2)
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#define LAN91C96_ACK_RX_OVRN_INT (0x1U << 4)
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#define LAN91C96_ACK_ERCV_INT (0x1U << 6)
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/*
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****************************************************************************
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* Interrupt Mask Register - Bank 2 - Offset 13
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****************************************************************************
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*/
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#define LAN91C96_MSK_RCV_INT (0x1U << 0)
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#define LAN91C96_MSK_TX_INT (0x1U << 1)
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#define LAN91C96_MSK_TX_EMPTY_INT (0x1U << 2)
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#define LAN91C96_MSK_ALLOC_INT (0x1U << 3)
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#define LAN91C96_MSK_RX_OVRN_INT (0x1U << 4)
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#define LAN91C96_MSK_EPH_INT (0x1U << 5)
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#define LAN91C96_MSK_ERCV_INT (0x1U << 6)
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#define LAN91C96_MSK_TX_IDLE_INT (0x1U << 7)
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/*
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****************************************************************************
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* Bank 3 Register Map in I/O Space
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**************************************************************************
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*/
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#define LAN91C96_MGMT_MDO (0x1U << 0)
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#define LAN91C96_MGMT_MDI (0x1U << 1)
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#define LAN91C96_MGMT_MCLK (0x1U << 2)
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#define LAN91C96_MGMT_MDOE (0x1U << 3)
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#define LAN91C96_MGMT_LOW_ID (0x3U << 4)
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#define LAN91C96_MGMT_IOS0 (0x1U << 8)
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#define LAN91C96_MGMT_IOS1 (0x1U << 9)
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#define LAN91C96_MGMT_IOS2 (0x1U << 10)
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#define LAN91C96_MGMT_nXNDEC (0x1U << 11)
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#define LAN91C96_MGMT_HIGH_ID (0x3U << 12)
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/*
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****************************************************************************
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* Revision Register - Bank 3 - Offset 10
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****************************************************************************
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*/
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#define LAN91C96_REV_REVID (0xFU << 0)
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#define LAN91C96_REV_CHIPID (0xFU << 4)
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/*
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****************************************************************************
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* Early RCV Register - Bank 3 - Offset 12
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****************************************************************************
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*/
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#define LAN91C96_ERCV_THRESHOLD (0x1FU << 0)
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#define LAN91C96_ERCV_RCV_DISCRD (0x1U << 7)
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/*
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****************************************************************************
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* PCMCIA Configuration Registers
|
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****************************************************************************
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*/
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#define LAN91C96_ECOR 0x8000 /* Ethernet Configuration Register */
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#define LAN91C96_ECSR 0x8002 /* Ethernet Configuration and Status */
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/*
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****************************************************************************
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|
* PCMCIA Ethernet Configuration Option Register (ECOR)
|
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****************************************************************************
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*/
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#define LAN91C96_ECOR_ENABLE (0x1U << 0)
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#define LAN91C96_ECOR_WR_ATTRIB (0x1U << 2)
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#define LAN91C96_ECOR_LEVEL_REQ (0x1U << 6)
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#define LAN91C96_ECOR_SRESET (0x1U << 7)
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|
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/*
|
|
****************************************************************************
|
|
* PCMCIA Ethernet Configuration and Status Register (ECSR)
|
|
****************************************************************************
|
|
*/
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#define LAN91C96_ECSR_INTR (0x1U << 1)
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#define LAN91C96_ECSR_PWRDWN (0x1U << 2)
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#define LAN91C96_ECSR_IOIS8 (0x1U << 5)
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|
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/*
|
|
****************************************************************************
|
|
* Receive Frame Status Word - See page 38 of the LAN91C96 specification.
|
|
****************************************************************************
|
|
*/
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#define LAN91C96_TOO_SHORT (0x1U << 10)
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#define LAN91C96_TOO_LONG (0x1U << 11)
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#define LAN91C96_ODD_FRM (0x1U << 12)
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#define LAN91C96_BAD_CRC (0x1U << 13)
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#define LAN91C96_BROD_CAST (0x1U << 14)
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#define LAN91C96_ALGN_ERR (0x1U << 15)
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|
#define FRAME_FILTER (LAN91C96_TOO_SHORT | LAN91C96_TOO_LONG | LAN91C96_BAD_CRC | LAN91C96_ALGN_ERR)
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|
|
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/*
|
|
****************************************************************************
|
|
* Default MAC Address
|
|
****************************************************************************
|
|
*/
|
|
#define MAC_DEF_HI 0x0800
|
|
#define MAC_DEF_MED 0x3333
|
|
#define MAC_DEF_LO 0x0100
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|
|
|
/*
|
|
****************************************************************************
|
|
* Default I/O Signature - 0x33
|
|
****************************************************************************
|
|
*/
|
|
#define LAN91C96_LOW_SIGNATURE (0x33U << 0)
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|
#define LAN91C96_HIGH_SIGNATURE (0x33U << 8)
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|
#define LAN91C96_SIGNATURE (LAN91C96_HIGH_SIGNATURE | LAN91C96_LOW_SIGNATURE)
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|
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#define LAN91C96_MAX_PAGES 6 /* Maximum number of 256 pages. */
|
|
#define ETHERNET_MAX_LENGTH 1514
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|
|
|
|
|
/*-------------------------------------------------------------------------
|
|
* I define some macros to make it easier to do somewhat common
|
|
* or slightly complicated, repeated tasks.
|
|
*-------------------------------------------------------------------------
|
|
*/
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|
|
|
/* select a register bank, 0 to 3 */
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|
|
|
#define SMC_SELECT_BANK(edev, x) { SMC_outw(edev, x, LAN91C96_BANK_SELECT); }
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|
|
|
/* this enables an interrupt in the interrupt mask register */
|
|
#define SMC_ENABLE_INT(edev, x) {\
|
|
unsigned char mask;\
|
|
SMC_SELECT_BANK(edev, 2);\
|
|
mask = SMC_inb(edev, LAN91C96_INT_MASK);\
|
|
mask |= (x);\
|
|
SMC_outb(edev, mask, LAN91C96_INT_MASK); \
|
|
}
|
|
|
|
/* this disables an interrupt from the interrupt mask register */
|
|
|
|
#define SMC_DISABLE_INT(edev, x) {\
|
|
unsigned char mask;\
|
|
SMC_SELECT_BANK(edev, 2);\
|
|
mask = SMC_inb(edev, LAN91C96_INT_MASK);\
|
|
mask &= ~(x);\
|
|
SMC_outb(edev, mask, LAN91C96_INT_MASK); \
|
|
}
|
|
|
|
/*----------------------------------------------------------------------
|
|
* Define the interrupts that I want to receive from the card
|
|
*
|
|
* I want:
|
|
* LAN91C96_IST_EPH_INT, for nasty errors
|
|
* LAN91C96_IST_RCV_INT, for happy received packets
|
|
* LAN91C96_IST_RX_OVRN_INT, because I have to kick the receiver
|
|
*-------------------------------------------------------------------------
|
|
*/
|
|
#define SMC_INTERRUPT_MASK (LAN91C96_IST_EPH_INT | LAN91C96_IST_RX_OVRN_INT | LAN91C96_IST_RCV_INT)
|
|
|
|
#endif /* _LAN91C96_H_ */
|