mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
46 lines
1.3 KiB
C
46 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2011
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* Linaro
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* Linus Walleij <linus.walleij@linaro.org>
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* Register definitions for the External Bus Interface (EBI)
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* found in the ARM Integrator AP and CP reference designs
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*/
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#ifndef __ARM_EBI_H
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#define __ARM_EBI_H
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#define EBI_BASE 0x12000000
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#define EBI_CSR0_REG 0x00 /* CS0 = Boot ROM */
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#define EBI_CSR1_REG 0x04 /* CS1 = Flash */
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#define EBI_CSR2_REG 0x08 /* CS2 = SSRAM */
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#define EBI_CSR3_REG 0x0C /* CS3 = Expansion memory */
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/*
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* The four upper bits are the waitstates for each chip select
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* 0x00 = 2 cycles, 0x10 = 3 cycles, ... 0xe0 = 16 cycles, 0xf0 = 16 cycles
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*/
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#define EBI_CSR_WAIT_MASK 0xF0
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/* Whether memory is synchronous or asynchronous */
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#define EBI_CSR_SYNC_MASK 0xF7
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#define EBI_CSR_ASYNC 0x00
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#define EBI_CSR_SYNC 0x08
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/* Whether memory is write enabled or not */
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#define EBI_CSR_WREN_MASK 0xFB
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#define EBI_CSR_WREN_DISABLE 0x00
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#define EBI_CSR_WREN_ENABLE 0x04
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/* Memory bit width for each chip select */
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#define EBI_CSR_MEMSIZE_MASK 0xFC
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#define EBI_CSR_MEMSIZE_8BIT 0x00
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#define EBI_CSR_MEMSIZE_16BIT 0x01
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#define EBI_CSR_MEMSIZE_32BIT 0x02
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/*
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* The lock register need to be written with 0xa05f before anything in the
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* EBI can be changed.
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*/
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#define EBI_LOCK_REG 0x20
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#define EBI_UNLOCK_MAGIC 0xA05F
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#endif
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