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https://github.com/brain-hackers/u-boot-brain
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5e5097c110
1) Add new SerDes1 protocols having Aurora in them 2) Add VSC cross point connections for Aurora to work with CPRI and SGMIIs 3) Configure VSC crossbar switch to connect SerDes1 lanes to aurora on board, by checking SerDes1 protocols 4) SerDes1 Refclks have been set properly to make Aurora, CPRI and SGMIIs to work together properly Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
74 lines
2.3 KiB
C
74 lines
2.3 KiB
C
/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CROSSBAR_CONNECTIONS_H__
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#define __CROSSBAR_CONNECTIONS_H__
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#define NUM_CON_VSC3316 8
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#define NUM_CON_VSC3308 4
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static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10},
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{5, 11}, {4, 5}, {2, 6}, {12, 9} };
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static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
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{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
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static int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
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{7, 8}, {9, 0}, {2, 14}, {12, 15},
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{-1, -1}, {-1, -1} };
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static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1},
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{7, 8}, {9, 0}, {5, 14}, {4, 15},
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{-1, -1}, {-1, -1} };
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static int8_t vsc16_tx_sfp_sgmii_aurora[8][2] = { {15, 7}, {0, 1},
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{7, 8}, {9, 0}, {5, 14},
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{4, 15}, {2, 12}, {12, 13} };
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#ifdef CONFIG_PPC_B4420
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static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
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{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
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#endif
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static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1},
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{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
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static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9},
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{11, 11}, {5, 10}, {6, 3}, {9, 12} };
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static int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9},
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{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
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static int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1},
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{7, 8}, {1, 9}, {14, 3}, {15, 12},
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{-1, -1}, {-1, -1} };
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static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1},
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{7, 8}, {1, 9}, {14, 11}, {15, 10},
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{-1, -1}, {-1, -1} };
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static int8_t vsc16_rx_sfp_sgmii_aurora[8][2] = { {8, 15}, {0, 1},
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{7, 8}, {1, 9}, {14, 11},
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{15, 10}, {13, 3}, {12, 12} };
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#ifdef CONFIG_PPC_B4420
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static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
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{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
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#endif
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static const int8_t vsc16_rx_aurora[8][2] = { {13, 3}, {12, 12}, {-1, -1},
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{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
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static const int8_t vsc08_tx_amc[4][2] = { {2, 2}, {3, 3}, {7, 4}, {1, 5} };
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static const int8_t vsc08_tx_sfp[4][2] = { {2, 1}, {3, 0}, {7, 6}, {1, 7} };
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static const int8_t vsc08_rx_amc[4][2] = { {2, 3}, {3, 4}, {4, 7}, {5, 1} };
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static const int8_t vsc08_rx_sfp[4][2] = { {1, 3}, {0, 4}, {6, 7}, {7, 1} };
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#endif
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