mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
3a187cff7a
LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
190 lines
3.2 KiB
Plaintext
190 lines
3.2 KiB
Plaintext
config SYS_FSL_DDR
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bool
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help
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Select Freescale General DDR driver, shared between most Freescale
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PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
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based Layerscape SoCs (such as ls2080a).
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config SYS_FSL_MMDC
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bool
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help
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Select Freescale Multi Mode DDR controller (MMDC).
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config SYS_FSL_DDR_BE
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bool
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help
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Access DDR registers in big-endian
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config SYS_FSL_DDR_LE
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bool
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help
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Access DDR registers in little-endian
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config FSL_DDR_BIST
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bool
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config FSL_DDR_INTERACTIVE
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bool
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config FSL_DDR_SYNC_REFRESH
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bool
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config FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
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bool
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menu "Freescale DDR controllers"
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depends on SYS_FSL_DDR
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config SYS_NUM_DDR_CTLRS
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int "Maximum DDR controllers"
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default 3 if ARCH_LS2080A || \
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ARCH_T4240
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default 2 if ARCH_B4860 || \
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ARCH_BSC9132 || \
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ARCH_MPC8572 || \
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ARCH_MPC8641 || \
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ARCH_P4080 || \
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ARCH_P5020 || \
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ARCH_P5040 || \
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ARCH_LX2160A || \
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ARCH_LX2162A || \
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ARCH_T4160
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default 1
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config SYS_FSL_DDR_VER
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int
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default 50 if SYS_FSL_DDR_VER_50
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default 47 if SYS_FSL_DDR_VER_47
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default 46 if SYS_FSL_DDR_VER_46
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default 44 if SYS_FSL_DDR_VER_44
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config SYS_FSL_DDR_VER_50
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bool
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config SYS_FSL_DDR_VER_47
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bool
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config SYS_FSL_DDR_VER_46
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bool
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config SYS_FSL_DDR_VER_44
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bool
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config SYS_FSL_DDRC_GEN1
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bool
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help
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Enable Freescale DDR controller.
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config SYS_FSL_DDRC_GEN2
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bool
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depends on !MPC86xx
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help
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Enable Freescale DDR2 controller.
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config SYS_FSL_DDRC_86XX_GEN2
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bool
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depends on MPC86xx
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help
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Enable Freescale DDR2 controller for MPC86xx SoCs.
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config SYS_FSL_DDRC_GEN3
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bool
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depends on PPC
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help
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Enable Freescale DDR3 controller for PowerPC SoCs.
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config SYS_FSL_DDRC_ARM_GEN3
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bool
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depends on ARM
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help
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Enable Freescale DDR3 controller for ARM SoCs.
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config SYS_FSL_DDRC_GEN4
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bool
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help
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Enable Freescale DDR4 controller.
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config SYS_FSL_HAS_DDR4
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bool
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config SYS_FSL_HAS_DDR3
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bool
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config SYS_FSL_HAS_DDR2
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bool
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config SYS_FSL_HAS_DDR1
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bool
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choice
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prompt "DDR technology"
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default SYS_FSL_DDR4 if SYS_FSL_HAS_DDR4
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default SYS_FSL_DDR3 if SYS_FSL_HAS_DDR3
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default SYS_FSL_DDR2 if SYS_FSL_HAS_DDR2
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default SYS_FSL_DDR1 if SYS_FSL_HAS_DDR1
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config SYS_FSL_DDR4
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bool "Freescale DDR4 controller"
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depends on SYS_FSL_HAS_DDR4
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select SYS_FSL_DDRC_GEN4
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config SYS_FSL_DDR3
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bool "Freescale DDR3 controller"
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depends on SYS_FSL_HAS_DDR3
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select SYS_FSL_DDRC_GEN3 if PPC
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select SYS_FSL_DDRC_ARM_GEN3 if ARM
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config SYS_FSL_DDR2
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bool "Freescale DDR2 controller"
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depends on SYS_FSL_HAS_DDR2
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select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
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select SYS_FSL_DDRC_86XX_GEN2 if MPC86xx
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config SYS_FSL_DDR1
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bool "Freescale DDR1 controller"
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depends on SYS_FSL_HAS_DDR1
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select SYS_FSL_DDRC_GEN1
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endchoice
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endmenu
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config SYS_FSL_ERRATUM_A008378
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bool
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config SYS_FSL_ERRATUM_A008109
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bool
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config SYS_FSL_ERRATUM_A008511
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bool
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config SYS_FSL_ERRATUM_A009663
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bool
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config SYS_FSL_ERRATUM_A009801
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bool
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config SYS_FSL_ERRATUM_A009803
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bool
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config SYS_FSL_ERRATUM_A009942
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bool
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config SYS_FSL_ERRATUM_A010165
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bool
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config SYS_FSL_ERRATUM_NMG_DDR120
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bool
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config SYS_FSL_ERRATUM_DDR_115
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bool
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config SYS_FSL_ERRATUM_DDR111_DDR134
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bool
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config SYS_FSL_ERRATUM_DDR_A003
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bool
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config SYS_FSL_ERRATUM_DDR_A003474
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bool
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