mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
6f6b7cfa89
This converts the following to Kconfig: CONFIG_CONS_INDEX We have existing entries for this option in a number of places, with different guards on them. They're also sometimes used for things not directly inside of the serial driver. First, introduce a new symbol to guard the use of CONFIG_CONS_INDEX, so that in the case where we don't need this for the serial driver, but for some other use, we can still do it. Next, consolidate all of these into the single entry in drivers/serial/Kconfig. Finally, introduce CONS_INDEX_[023456] so that we can imply a correct value here to make the defconfig side of this smaller. Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Rework a lot of the logic here, such that I took authorship from Adam, but kept his S-o-B line] Signed-off-by: Tom Rini <trini@konsulko.com>
868 lines
30 KiB
C
868 lines
30 KiB
C
/*
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* Copyright 2013-2015 Arcturus Networks, Inc.
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* http://www.arcturusnetworks.com/products/ucp1020/
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* based on include/configs/p1_p2_rdb_pc.h
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* original copyright follows:
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* QorIQ uCP1020-xx boards configuration file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
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#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
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#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
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#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
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#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
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#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
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#if defined(CONFIG_TARTGET_UCP1020T1)
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#define CONFIG_UCP1020_REV_1_3
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#define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
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#define CONFIG_TSEC_ENET
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#define CONFIG_TSEC1
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#define CONFIG_TSEC3
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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#define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
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#define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
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#define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
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#define CONFIG_IPADDR 10.80.41.229
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#define CONFIG_SERVERIP 10.80.41.227
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#define CONFIG_NETMASK 255.255.252.0
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#define CONFIG_ETHPRIME "eTSEC3"
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#ifndef CONFIG_SPI_FLASH
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#endif
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#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
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#define CONFIG_SYS_L2_SIZE (256 << 10)
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#define CONFIG_LAST_STAGE_INIT
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#endif
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#if defined(CONFIG_TARGET_UCP1020)
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#define CONFIG_UCP1020
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#define CONFIG_UCP1020_REV_1_3
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#define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
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#define CONFIG_TSEC_ENET
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#define CONFIG_TSEC1
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#define CONFIG_TSEC2
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#define CONFIG_TSEC3
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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#define CONFIG_HAS_ETH2
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#define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
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#define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
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#define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
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#define CONFIG_IPADDR 192.168.1.81
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#define CONFIG_IPADDR1 192.168.1.82
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#define CONFIG_IPADDR2 192.168.1.83
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#define CONFIG_SERVERIP 192.168.1.80
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#define CONFIG_GATEWAYIP 102.168.1.1
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_ETHPRIME "eTSEC1"
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#ifndef CONFIG_SPI_FLASH
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#endif
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#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
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#define CONFIG_SYS_L2_SIZE (256 << 10)
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#define CONFIG_LAST_STAGE_INIT
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#endif
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#ifdef CONFIG_SDCARD
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#define CONFIG_RAMBOOT_SDCARD
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#define CONFIG_SYS_RAMBOOT
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#define CONFIG_SYS_EXTRA_ENV_RELOC
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#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
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#endif
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#ifdef CONFIG_SPIFLASH
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#define CONFIG_RAMBOOT_SPIFLASH
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#define CONFIG_SYS_RAMBOOT
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#define CONFIG_SYS_EXTRA_ENV_RELOC
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#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
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#endif
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#define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
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#ifndef CONFIG_RESET_VECTOR_ADDRESS
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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#ifndef CONFIG_SYS_MONITOR_BASE
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#endif
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#define CONFIG_MP
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_SYS_SATA_MAX_DEVICE 2
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#define CONFIG_LBA48
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#define CONFIG_SYS_CLK_FREQ 66666666
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#define CONFIG_DDR_CLK_FREQ 66666666
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#define CONFIG_HWCONFIG
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_L2_CACHE
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#define CONFIG_BTB
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#define CONFIG_ENABLE_36BIT_PHYS
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#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x1fffffff
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#define CONFIG_SYS_CCSRBAR 0xffe00000
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#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
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/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
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SPL code*/
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
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#endif
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/* DDR Setup */
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#define CONFIG_DDR_ECC_ENABLE
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#ifndef CONFIG_DDR_ECC_ENABLE
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#define CONFIG_SYS_DDR_RAW_TIMING
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#define CONFIG_DDR_SPD
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#endif
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#define CONFIG_SYS_SPD_BUS_NUM 1
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#undef CONFIG_FSL_DDR_INTERACTIVE
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#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
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#define CONFIG_CHIP_SELECTS_PER_CTRL 1
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#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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/* Default settings for DDR3 */
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
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#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
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#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
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#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
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#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
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#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
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#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
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#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
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#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
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#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
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#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
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#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
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#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
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#define CONFIG_SYS_DDR_RCW_1 0x00000000
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#define CONFIG_SYS_DDR_RCW_2 0x00000000
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#ifdef CONFIG_DDR_ECC_ENABLE
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#define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
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#else
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#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
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#endif
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#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
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#define CONFIG_SYS_DDR_TIMING_4 0x00220001
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#define CONFIG_SYS_DDR_TIMING_5 0x03402400
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#define CONFIG_SYS_DDR_TIMING_3 0x00020000
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#define CONFIG_SYS_DDR_TIMING_0 0x00330004
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#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
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#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
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#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
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#define CONFIG_SYS_DDR_MODE_1 0x40461520
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#define CONFIG_SYS_DDR_MODE_2 0x8000c000
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#define CONFIG_SYS_DDR_INTERVAL 0x0C300000
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#undef CONFIG_CLOCKS_IN_MHZ
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/*
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* Memory map
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*
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* 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
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* 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
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* 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
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* 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
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* (early boot only)
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* 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
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* 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
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* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
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*/
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/*
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* Local Bus Definitions
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*/
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
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#define CONFIG_SYS_FLASH_BASE 0xec000000
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
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| BR_PS_16 | BR_V)
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#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
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#define CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#undef CONFIG_SYS_FLASH_CHECKSUM
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
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#define CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
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/* Initial L1 address */
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
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/* Size of used area in RAM */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
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#define CONFIG_SYS_PMC_BASE 0xff980000
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#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
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#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
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BR_PS_8 | BR_V)
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#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
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OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
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OR_GPCM_EAD)
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#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
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#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
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#ifdef CONFIG_NAND_FSL_ELBC
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#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
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#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
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#endif
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/* Serial Port - controlled on board with jumper J8
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* open - index 2
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* shorted - index 1
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*/
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
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#define CONFIG_NS16550_MIN_FUNCTIONS
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#endif
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_FSL_I2C2_SPEED 400000
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
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#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
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#define CONFIG_RTC_DS1337
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#define CONFIG_RTC_DS1337_NOOSC
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
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#define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
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#define CONFIG_SYS_I2C_IDT6V49205B 0x69
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/*
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* eSPI - Enhanced SPI
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*/
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#define CONFIG_HARD_SPI
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#define CONFIG_SF_DEFAULT_SPEED 10000000
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
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#if defined(CONFIG_PCI)
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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/* controller 2, direct to uli, tgtid 2, Base address 9000 */
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#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
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#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
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#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
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#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
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#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
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#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
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/* controller 1, Slot 2, tgtid 1, Base address a000 */
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#define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
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#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
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#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#endif /* CONFIG_PCI */
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/*
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* Environment
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*/
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#ifdef CONFIG_ENV_FIT_UCBOOT
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000)
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#define CONFIG_ENV_SIZE 0x20000
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
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#else
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#define CONFIG_ENV_SPI_BUS 0
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#define CONFIG_ENV_SPI_CS 0
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#define CONFIG_ENV_SPI_MAX_HZ 10000000
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#define CONFIG_ENV_SPI_MODE 0
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#ifdef CONFIG_RAMBOOT_SPIFLASH
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#define CONFIG_ENV_SIZE 0x3000 /* 12KB */
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#define CONFIG_ENV_OFFSET 0x2000 /* 8KB */
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#define CONFIG_ENV_SECT_SIZE 0x1000
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#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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#endif
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#elif defined(CONFIG_RAMBOOT_SDCARD)
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#define CONFIG_FSL_FIXED_MMC_LOCATION
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#elif defined(CONFIG_SYS_RAMBOOT)
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
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#define CONFIG_ENV_SIZE 0x2000
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#else
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#define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE)
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
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#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
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#define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000)
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#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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#endif
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#endif
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#endif /* CONFIG_ENV_FIT_UCBOOT */
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#define CONFIG_LOADS_ECHO /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
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/*
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* USB
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*/
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#define CONFIG_HAS_FSL_DR_USB
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#if defined(CONFIG_HAS_FSL_DR_USB)
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#ifdef CONFIG_USB_EHCI_HCD
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#define CONFIG_USB_EHCI_FSL
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#endif
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#endif
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#ifdef CONFIG_MMC
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#define CONFIG_FSL_ESDHC
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#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
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#define CONFIG_MMC_SPI
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#endif
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/* Misc Extra Settings */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 64 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Environment Configuration
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*/
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#if defined(CONFIG_TSEC_ENET)
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#if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3)
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#else
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#error "UCP1020 module revision is not defined !!!"
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#endif
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#define CONFIG_BOOTP_SERVERIP
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#define CONFIG_MII /* MII PHY management */
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#define CONFIG_TSEC1_NAME "eTSEC1"
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#define CONFIG_TSEC2_NAME "eTSEC2"
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#define CONFIG_TSEC3_NAME "eTSEC3"
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#define TSEC1_PHY_ADDR 4
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#define TSEC2_PHY_ADDR 0
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#define TSEC2_PHY_ADDR_SGMII 0x00
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#define TSEC3_PHY_ADDR 6
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#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC3_PHYIDX 0
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#endif
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#define CONFIG_HOSTNAME UCP1020
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#define CONFIG_ROOTPATH "/opt/nfsroot"
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
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/* default location for tftp and bootm */
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#define CONFIG_LOADADDR 1000000
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#if defined(CONFIG_DONGLE)
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootcmd=run prog_spi_mbrbootcramfs\0" \
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"bootfile=uImage\0" \
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"consoledev=ttyS0\0" \
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"cramfsfile=image.cramfs\0" \
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"dtbaddr=0x00c00000\0" \
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"dtbfile=image.dtb\0" \
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"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
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"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
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"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
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"fileaddr=0x01000000\0" \
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"filesize=0x00080000\0" \
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"flashmbr=sf probe 0; " \
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"tftp $loadaddr $mbr; " \
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"sf erase $mbr_offset +$filesize; " \
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"sf write $loadaddr $mbr_offset $filesize\0" \
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"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
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"protect off $nor_recoveryaddr +$filesize; " \
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"erase $nor_recoveryaddr +$filesize; " \
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"cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
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"protect on $nor_recoveryaddr +$filesize\0 " \
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"flashuboot=tftp $ubootaddr $ubootfile; " \
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"protect off $nor_ubootaddr +$filesize; " \
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"erase $nor_ubootaddr +$filesize; " \
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"cp.b $ubootaddr $nor_ubootaddr $filesize; " \
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"protect on $nor_ubootaddr +$filesize\0 " \
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"flashworking=tftp $workingaddr $cramfsfile; " \
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"protect off $nor_workingaddr +$filesize; " \
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"erase $nor_workingaddr +$filesize; " \
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"cp.b $workingaddr $nor_workingaddr $filesize; " \
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"protect on $nor_workingaddr +$filesize\0 " \
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"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
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"kerneladdr=0x01100000\0" \
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"kernelfile=uImage\0" \
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"loadaddr=0x01000000\0" \
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"mbr=uCP1020d.mbr\0" \
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"mbr_offset=0x00000000\0" \
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"mmbr=uCP1020Quiet.mbr\0" \
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"mmcpart=0:2\0" \
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"mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
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"mmc erase 1 1; " \
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"mmc write $loadaddr 1 1\0" \
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"mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
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"mmc erase 0x40 0x400; " \
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"mmc write $loadaddr 0x40 0x400\0" \
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"netdev=eth0\0" \
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"nor_recoveryaddr=0xEC0A0000\0" \
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"nor_ubootaddr=0xEFF80000\0" \
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"nor_workingaddr=0xECFA0000\0" \
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"norbootrecovery=setenv bootargs $recoverybootargs" \
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" console=$consoledev,$baudrate $othbootargs; " \
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"run norloadrecovery; " \
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"bootm $kerneladdr - $dtbaddr\0" \
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"norbootworking=setenv bootargs $workingbootargs" \
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" console=$consoledev,$baudrate $othbootargs; " \
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"run norloadworking; " \
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"bootm $kerneladdr - $dtbaddr\0" \
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"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
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"setenv cramfsaddr $nor_recoveryaddr; " \
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"cramfsload $dtbaddr $dtbfile; " \
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"cramfsload $kerneladdr $kernelfile\0" \
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"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
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"setenv cramfsaddr $nor_workingaddr; " \
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"cramfsload $dtbaddr $dtbfile; " \
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"cramfsload $kerneladdr $kernelfile\0" \
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"prog_spi_mbr=run spi__mbr\0" \
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"prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
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"prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
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"run spi__cramfs\0" \
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"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
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" console=$consoledev,$baudrate $othbootargs; " \
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"tftp $rootfsaddr $rootfsfile; " \
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"tftp $loadaddr $kernelfile; " \
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"tftp $dtbaddr $dtbfile; " \
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"bootm $loadaddr $rootfsaddr $dtbaddr\0" \
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"ramdisk_size=120000\0" \
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"ramdiskfile=rootfs.ext2.gz.uboot\0" \
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"recoveryaddr=0x02F00000\0" \
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"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
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"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
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"mw.l 0xffe0f008 0x00400000\0" \
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"rootfsaddr=0x02F00000\0" \
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"rootfsfile=rootfs.ext2.gz.uboot\0" \
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"rootpath=/opt/nfsroot\0" \
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"spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
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"protect off 0xeC000000 +$filesize; " \
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"erase 0xEC000000 +$filesize; " \
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"cp.b $loadaddr 0xEC000000 $filesize; " \
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"cmp.b $loadaddr 0xEC000000 $filesize; " \
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"protect on 0xeC000000 +$filesize\0" \
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"spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
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"protect off 0xeFF80000 +$filesize; " \
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"erase 0xEFF80000 +$filesize; " \
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"cp.b $loadaddr 0xEFF80000 $filesize; " \
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"cmp.b $loadaddr 0xEFF80000 $filesize; " \
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"protect on 0xeFF80000 +$filesize\0" \
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"spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
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"sf probe 0; sf erase 0x8000 +$filesize; " \
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"sf write $loadaddr 0x8000 $filesize\0" \
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"spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
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"protect off 0xec0a0000 +$filesize; " \
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"erase 0xeC0A0000 +$filesize; " \
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"cp.b $loadaddr 0xeC0A0000 $filesize; " \
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"protect on 0xec0a0000 +$filesize\0" \
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"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
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"sf probe 1; sf erase 0 +$filesize; " \
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"sf write $loadaddr 0 $filesize\0" \
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"spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
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"sf probe 0; sf erase 0 +$filesize; " \
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"sf write $loadaddr 0 $filesize\0" \
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"tftpflash=tftpboot $loadaddr $uboot; " \
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"protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
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"erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
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"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
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"protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
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"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
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"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
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"ubootaddr=0x01000000\0" \
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"ubootfile=u-boot.bin\0" \
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"ubootd=u-boot4dongle.bin\0" \
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"upgrade=run flashworking\0" \
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"usb_phy_type=ulpi\0 " \
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"workingaddr=0x02F00000\0" \
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"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
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#else
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#if defined(CONFIG_UCP1020T1)
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
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"bootfile=uImage\0" \
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"consoledev=ttyS0\0" \
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"cramfsfile=image.cramfs\0" \
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"dtbaddr=0x00c00000\0" \
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"dtbfile=image.dtb\0" \
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"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
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"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
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"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
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"fileaddr=0x01000000\0" \
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"filesize=0x00080000\0" \
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"flashmbr=sf probe 0; " \
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"tftp $loadaddr $mbr; " \
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"sf erase $mbr_offset +$filesize; " \
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"sf write $loadaddr $mbr_offset $filesize\0" \
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"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
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"protect off $nor_recoveryaddr +$filesize; " \
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"erase $nor_recoveryaddr +$filesize; " \
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"cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
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"protect on $nor_recoveryaddr +$filesize\0 " \
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"flashuboot=tftp $ubootaddr $ubootfile; " \
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"protect off $nor_ubootaddr +$filesize; " \
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"erase $nor_ubootaddr +$filesize; " \
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"cp.b $ubootaddr $nor_ubootaddr $filesize; " \
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"protect on $nor_ubootaddr +$filesize\0 " \
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"flashworking=tftp $workingaddr $cramfsfile; " \
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"protect off $nor_workingaddr +$filesize; " \
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"erase $nor_workingaddr +$filesize; " \
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"cp.b $workingaddr $nor_workingaddr $filesize; " \
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"protect on $nor_workingaddr +$filesize\0 " \
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"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
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"kerneladdr=0x01100000\0" \
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"kernelfile=uImage\0" \
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"loadaddr=0x01000000\0" \
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"mbr=uCP1020.mbr\0" \
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"mbr_offset=0x00000000\0" \
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"netdev=eth0\0" \
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"nor_recoveryaddr=0xEC0A0000\0" \
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"nor_ubootaddr=0xEFF80000\0" \
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"nor_workingaddr=0xECFA0000\0" \
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"norbootrecovery=setenv bootargs $recoverybootargs" \
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" console=$consoledev,$baudrate $othbootargs; " \
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"run norloadrecovery; " \
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"bootm $kerneladdr - $dtbaddr\0" \
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"norbootworking=setenv bootargs $workingbootargs" \
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" console=$consoledev,$baudrate $othbootargs; " \
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"run norloadworking; " \
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"bootm $kerneladdr - $dtbaddr\0" \
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"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
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"setenv cramfsaddr $nor_recoveryaddr; " \
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"cramfsload $dtbaddr $dtbfile; " \
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"cramfsload $kerneladdr $kernelfile\0" \
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"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
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"setenv cramfsaddr $nor_workingaddr; " \
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"cramfsload $dtbaddr $dtbfile; " \
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"cramfsload $kerneladdr $kernelfile\0" \
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"othbootargs=quiet\0" \
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"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
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" console=$consoledev,$baudrate $othbootargs; " \
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"tftp $rootfsaddr $rootfsfile; " \
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"tftp $loadaddr $kernelfile; " \
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"tftp $dtbaddr $dtbfile; " \
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"bootm $loadaddr $rootfsaddr $dtbaddr\0" \
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"ramdisk_size=120000\0" \
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"ramdiskfile=rootfs.ext2.gz.uboot\0" \
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"recoveryaddr=0x02F00000\0" \
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"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
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"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
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"mw.l 0xffe0f008 0x00400000\0" \
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"rootfsaddr=0x02F00000\0" \
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"rootfsfile=rootfs.ext2.gz.uboot\0" \
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"rootpath=/opt/nfsroot\0" \
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"silent=1\0" \
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"tftpflash=tftpboot $loadaddr $uboot; " \
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"protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
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"erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
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"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
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"protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
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"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
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"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
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"ubootaddr=0x01000000\0" \
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"ubootfile=u-boot.bin\0" \
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"upgrade=run flashworking\0" \
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"workingaddr=0x02F00000\0" \
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"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
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|
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#else /* For Arcturus Modules */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootcmd=run norkernel\0" \
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"bootfile=uImage\0" \
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"consoledev=ttyS0\0" \
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"dtbaddr=0x00c00000\0" \
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"dtbfile=image.dtb\0" \
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"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
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"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
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"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
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"fileaddr=0x01000000\0" \
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"filesize=0x00080000\0" \
|
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"flashmbr=sf probe 0; " \
|
|
"tftp $loadaddr $mbr; " \
|
|
"sf erase $mbr_offset +$filesize; " \
|
|
"sf write $loadaddr $mbr_offset $filesize\0" \
|
|
"flashuboot=tftp $loadaddr $ubootfile; " \
|
|
"protect off $nor_ubootaddr0 +$filesize; " \
|
|
"erase $nor_ubootaddr0 +$filesize; " \
|
|
"cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
|
|
"protect on $nor_ubootaddr0 +$filesize; " \
|
|
"protect off $nor_ubootaddr1 +$filesize; " \
|
|
"erase $nor_ubootaddr1 +$filesize; " \
|
|
"cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
|
|
"protect on $nor_ubootaddr1 +$filesize\0 " \
|
|
"format0=protect off $part0base +$part0size; " \
|
|
"erase $part0base +$part0size\0" \
|
|
"format1=protect off $part1base +$part1size; " \
|
|
"erase $part1base +$part1size\0" \
|
|
"format2=protect off $part2base +$part2size; " \
|
|
"erase $part2base +$part2size\0" \
|
|
"format3=protect off $part3base +$part3size; " \
|
|
"erase $part3base +$part3size\0" \
|
|
"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
|
|
"kerneladdr=0x01100000\0" \
|
|
"kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
|
|
"kernelfile=uImage\0" \
|
|
"loadaddr=0x01000000\0" \
|
|
"mbr=uCP1020.mbr\0" \
|
|
"mbr_offset=0x00000000\0" \
|
|
"netdev=eth0\0" \
|
|
"nor_ubootaddr0=0xEC000000\0" \
|
|
"nor_ubootaddr1=0xEFF80000\0" \
|
|
"norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
|
|
"run norkernelload; " \
|
|
"bootm $kerneladdr - $dtbaddr\0" \
|
|
"norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
|
|
"setenv cramfsaddr $part0base; " \
|
|
"cramfsload $dtbaddr $dtbfile; " \
|
|
"cramfsload $kerneladdr $kernelfile\0" \
|
|
"part0base=0xEC100000\0" \
|
|
"part0size=0x00700000\0" \
|
|
"part1base=0xEC800000\0" \
|
|
"part1size=0x02000000\0" \
|
|
"part2base=0xEE800000\0" \
|
|
"part2size=0x00800000\0" \
|
|
"part3base=0xEF000000\0" \
|
|
"part3size=0x00F80000\0" \
|
|
"partENVbase=0xEC080000\0" \
|
|
"partENVsize=0x00080000\0" \
|
|
"program0=tftp part0-000000.bin; " \
|
|
"protect off $part0base +$filesize; " \
|
|
"erase $part0base +$filesize; " \
|
|
"cp.b $loadaddr $part0base $filesize; " \
|
|
"echo Verifying...; " \
|
|
"cmp.b $loadaddr $part0base $filesize\0" \
|
|
"program1=tftp part1-000000.bin; " \
|
|
"protect off $part1base +$filesize; " \
|
|
"erase $part1base +$filesize; " \
|
|
"cp.b $loadaddr $part1base $filesize; " \
|
|
"echo Verifying...; " \
|
|
"cmp.b $loadaddr $part1base $filesize\0" \
|
|
"program2=tftp part2-000000.bin; " \
|
|
"protect off $part2base +$filesize; " \
|
|
"erase $part2base +$filesize; " \
|
|
"cp.b $loadaddr $part2base $filesize; " \
|
|
"echo Verifying...; " \
|
|
"cmp.b $loadaddr $part2base $filesize\0" \
|
|
"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
|
|
" console=$consoledev,$baudrate $othbootargs; " \
|
|
"tftp $rootfsaddr $rootfsfile; " \
|
|
"tftp $loadaddr $kernelfile; " \
|
|
"tftp $dtbaddr $dtbfile; " \
|
|
"bootm $loadaddr $rootfsaddr $dtbaddr\0" \
|
|
"ramdisk_size=120000\0" \
|
|
"ramdiskfile=rootfs.ext2.gz.uboot\0" \
|
|
"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
|
|
"mw.l 0xffe0f008 0x00400000\0" \
|
|
"rootfsaddr=0x02F00000\0" \
|
|
"rootfsfile=rootfs.ext2.gz.uboot\0" \
|
|
"rootpath=/opt/nfsroot\0" \
|
|
"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
|
|
"sf probe 0; sf erase 0 +$filesize; " \
|
|
"sf write $loadaddr 0 $filesize\0" \
|
|
"spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
|
|
"protect off 0xeC000000 +$filesize; " \
|
|
"erase 0xEC000000 +$filesize; " \
|
|
"cp.b $loadaddr 0xEC000000 $filesize; " \
|
|
"cmp.b $loadaddr 0xEC000000 $filesize; " \
|
|
"protect on 0xeC000000 +$filesize\0" \
|
|
"tftpflash=tftpboot $loadaddr $uboot; " \
|
|
"protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
|
|
"erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
|
|
"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
|
|
"protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
|
|
"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
|
|
"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
|
|
"ubootfile=u-boot.bin\0" \
|
|
"upgrade=run flashuboot\0" \
|
|
"usb_phy_type=ulpi\0 " \
|
|
"boot_nfs= " \
|
|
"setenv bootargs root=/dev/nfs rw " \
|
|
"nfsroot=$serverip:$rootpath " \
|
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
|
"console=$consoledev,$baudrate $othbootargs;" \
|
|
"tftp $loadaddr $bootfile;" \
|
|
"tftp $fdtaddr $fdtfile;" \
|
|
"bootm $loadaddr - $fdtaddr\0" \
|
|
"boot_hd = " \
|
|
"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
|
|
"console=$consoledev,$baudrate $othbootargs;" \
|
|
"usb start;" \
|
|
"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
|
|
"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
|
|
"bootm $loadaddr - $fdtaddr\0" \
|
|
"boot_usb_fat = " \
|
|
"setenv bootargs root=/dev/ram rw " \
|
|
"console=$consoledev,$baudrate $othbootargs " \
|
|
"ramdisk_size=$ramdisk_size;" \
|
|
"usb start;" \
|
|
"fatload usb 0:2 $loadaddr $bootfile;" \
|
|
"fatload usb 0:2 $fdtaddr $fdtfile;" \
|
|
"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
|
|
"bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
|
|
"boot_usb_ext2 = " \
|
|
"setenv bootargs root=/dev/ram rw " \
|
|
"console=$consoledev,$baudrate $othbootargs " \
|
|
"ramdisk_size=$ramdisk_size;" \
|
|
"usb start;" \
|
|
"ext2load usb 0:4 $loadaddr $bootfile;" \
|
|
"ext2load usb 0:4 $fdtaddr $fdtfile;" \
|
|
"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
|
|
"bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
|
|
"boot_nor = " \
|
|
"setenv bootargs root=/dev/$jffs2nor rw " \
|
|
"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
|
|
"bootm $norbootaddr - $norfdtaddr\0 " \
|
|
"boot_ram = " \
|
|
"setenv bootargs root=/dev/ram rw " \
|
|
"console=$consoledev,$baudrate $othbootargs " \
|
|
"ramdisk_size=$ramdisk_size;" \
|
|
"tftp $ramdiskaddr $ramdiskfile;" \
|
|
"tftp $loadaddr $bootfile;" \
|
|
"tftp $fdtaddr $fdtfile;" \
|
|
"bootm $loadaddr $ramdiskaddr $fdtaddr\0"
|
|
|
|
#endif
|
|
#endif
|
|
|
|
#endif /* __CONFIG_H */
|