Lokesh Vutla ea8eff1fe0 arm: dra7xx: clock: Add the dplls data ... A new DPLL DDR is added in DRA7XX socs. Now clocks to EMIF CD is from DPLL DDR. So DPLL DDR should be locked before initializing RAM. Also adding other dpll data which are different from OMAP5 ES2.0. SYS_CLK running at 20MHz is introduced in DRA7xx socs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>		2013-03-11 11:06:11 -04:00
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arm720t	Tegra114: Add AVP (arm720t) files	2013-02-11 10:35:25 -07:00
arm920t	arm: Move lastinc to arch_global_data	2013-02-01 15:07:50 -05:00
arm925t	arm: remove useless code in start.S files	2013-01-08 22:14:54 +01:00
arm926ejs	Merge branch 'master' of git://git.denx.de/u-boot-arm	2013-02-12 10:18:31 -05:00
arm946es	arm: move C runtime setup code in crt0.S	2013-01-08 22:14:50 +01:00
arm1136	SPL: ONENAND: Fix some ONENAND related defines.	2013-03-08 16:41:14 -05:00
arm1176	arm: move C runtime setup code in crt0.S	2013-01-08 22:14:50 +01:00
arm_intcm	arm: move C runtime setup code in crt0.S	2013-01-08 22:14:50 +01:00
armv7	arm: dra7xx: clock: Add the dplls data	2013-03-11 11:06:11 -04:00
ixp	ixp: Move timestamp to arch_global_data	2013-02-01 15:07:50 -05:00
pxa	arm: Move lastinc to arch_global_data	2013-02-01 15:07:50 -05:00
s3c44b0	arm: move C runtime setup code in crt0.S	2013-01-08 22:14:50 +01:00
sa1100	arm: move C runtime setup code in crt0.S	2013-01-08 22:14:50 +01:00
tegra20-common	tegra: rename FUNCMUX_UART2_UARTB	2013-02-11 10:35:24 -07:00
tegra30-common	tegra30: add SBC1 to periph id mapping table	2013-02-11 10:35:24 -07:00
tegra114-common	Tegra114: Add common CPU (shared) files	2013-02-11 10:35:25 -07:00
tegra-common	Merge branch 'master' of git://git.denx.de/u-boot-arm	2013-02-12 10:18:31 -05:00
u-boot.lds	ARM: enhance u-boot.lds to detect over-sized SPL	2012-10-29 09:07:05 -07:00