mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-03 08:43:45 +09:00
06ae2b0ce8
Patch f33b9bd3
[arm: omap3: Enable clocks for peripherals only if they are used]
breaks SPL booting on Overo. Since some gpio inputs are
read to detect the board revision. But with this patch above, the
clocks to the GPIO subsystems are not enabled per default any more.
The GPIO banks need to be configured specifically now.
Signed-off-by: Ash Charles <ashcharles@gmail.com>
372 lines
11 KiB
C
372 lines
11 KiB
C
/*
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* Configuration settings for the Gumstix Overo board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_OMAP /* in a TI OMAP core */
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#define CONFIG_OMAP34XX /* which is a 34XX */
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#define CONFIG_OMAP3_OVERO /* working with overo */
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#define CONFIG_OMAP_GPIO
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#define CONFIG_OMAP_COMMON
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#define CONFIG_SDRC /* The chip has SDRC controller */
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#include <asm/arch/omap3.h>
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/*
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* Display CPU and Board information
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*/
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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/* Clock Defines */
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#define V_OSCK 26000000 /* Clock output from T2 */
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#define V_SCLK (V_OSCK >> 1)
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#define CONFIG_MISC_INIT_R
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_REVISION_TAG
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#define CONFIG_OF_LIBFDT
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
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/* Shift 128 << 15 provides 4 MiB heap to support UBI commands.
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* Shift 128 << 10 provides 128 KiB heap for limited-memory devices. */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 15))
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/*
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* Hardware drivers
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*/
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/*
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* NS16550 Configuration
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*/
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#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
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/*
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* select serial console configuration
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*/
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#define CONFIG_CONS_INDEX 3
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#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
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#define CONFIG_SERIAL3 3
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
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115200}
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#define CONFIG_GENERIC_MMC
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#define CONFIG_MMC
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#define CONFIG_OMAP_HSMMC
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#define CONFIG_DOS_PARTITION
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#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO Bank 2 */
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#define CONFIG_OMAP3_GPIO_3 /* GPIO64..95 is in GPIO Bank 3 */
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#define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO Bank 4 */
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#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO Bank 5 */
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#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO Bank 6 */
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/* commands to include */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_EXT2 /* EXT2 Support */
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#define CONFIG_CMD_FAT /* FAT support */
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#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
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#define CONFIG_CMD_I2C /* I2C serial bus support */
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#define CONFIG_CMD_MMC /* MMC support */
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#define CONFIG_CMD_NAND /* NAND support */
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#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
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#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
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#undef CONFIG_CMD_IMI /* iminfo */
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#undef CONFIG_CMD_IMLS /* List all found images */
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#undef CONFIG_CMD_NFS /* NFS support */
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#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_CMD_MTDPARTS /* MTD partition support */
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#define CONFIG_CMD_UBI /* UBI-formated MTD partition support */
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#define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */
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#define CONFIG_RBTREE /* required by CONFIG_CMD_UBI */
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#define CONFIG_LZO /* required by CONFIG_CMD_UBIFS */
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#define CONFIG_MTD_DEVICE /* required by CONFIG_CMD_MTDPARTS */
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#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */
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/* NAND block size is 128 KiB. Synchronize these values with
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* overo_nand_partitions in mach-omap2/board-overo.c in Linux:
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* xloader 4 * NAND_BLOCK_SIZE = 512 KiB
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* uboot 14 * NAND_BLOCK_SIZE = 1792 KiB
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* uboot environtment 2 * NAND_BLOCK_SIZE = 256 KiB
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* linux 64 * NAND_BLOCK_SIZE = 8 MiB
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* rootfs remainder
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*/
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#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
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#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \
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"512k(xloader)," \
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"1792k(u-boot)," \
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"256k(environ)," \
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"8m(linux)," \
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"-(rootfs)"
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#else /* CONFIG_CMD_NAND */
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#define MTDPARTS_DEFAULT
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#endif /* CONFIG_CMD_NAND */
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
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#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
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#define CONFIG_SYS_I2C_OMAP34XX
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/*
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* TWL4030
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*/
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#define CONFIG_TWL4030_POWER
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#define CONFIG_TWL4030_LED
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/*
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* Board NAND Info.
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*/
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#define CONFIG_SYS_NAND_QUIET_TEST
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#define CONFIG_NAND_OMAP_GPMC
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#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
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/* to access nand */
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#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
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/* to access nand */
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/* at CS0 */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
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/* devices */
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/* Environment information */
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#define CONFIG_BOOTDELAY 5
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"loadaddr=0x82000000\0" \
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"console=ttyO2,115200n8\0" \
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"mpurate=500\0" \
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"optargs=\0" \
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"vram=12M\0" \
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"dvimode=1024x768MR-16@60\0" \
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"defaultdisplay=dvi\0" \
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"mmcdev=0\0" \
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"mmcroot=/dev/mmcblk0p2 rw\0" \
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"mmcrootfstype=ext3 rootwait\0" \
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"nandroot=ubi0:rootfs ubi.mtd=4\0" \
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"nandrootfstype=ubifs\0" \
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"mtdparts=" MTDPARTS_DEFAULT "\0" \
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"mmcargs=setenv bootargs console=${console} " \
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"${optargs} " \
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"mpurate=${mpurate} " \
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"vram=${vram} " \
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"omapfb.mode=dvi:${dvimode} " \
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"omapdss.def_disp=${defaultdisplay} " \
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"root=${mmcroot} " \
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"rootfstype=${mmcrootfstype}\0" \
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"nandargs=setenv bootargs console=${console} " \
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"${optargs} " \
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"mpurate=${mpurate} " \
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"vram=${vram} " \
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"omapfb.mode=dvi:${dvimode} " \
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"omapdss.def_disp=${defaultdisplay} " \
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"root=${nandroot} " \
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"rootfstype=${nandrootfstype}\0" \
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"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source ${loadaddr}\0" \
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"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
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"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
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"env import -t ${loadaddr} ${filesize}\0" \
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"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"bootm ${loadaddr}\0" \
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"nandboot=echo Booting from nand ...; " \
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"run nandargs; " \
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"nand read ${loadaddr} linux; " \
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"bootm ${loadaddr}\0" \
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#define CONFIG_BOOTCOMMAND \
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"mmc dev ${mmcdev}; if mmc rescan; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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"if run loadbootenv; then " \
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"run importbootenv; " \
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"if test -n ${uenvcmd}; then " \
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"echo Running uenvcmd ...;" \
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"run uenvcmd;" \
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"fi;" \
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"fi;" \
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"if run loaduimage; then " \
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"run mmcboot; " \
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"else run nandboot; " \
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"fi; " \
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"fi; " \
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"else run nandboot; fi"
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#define CONFIG_AUTO_COMPLETE 1
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#define CONFIG_SYS_PROMPT "Overo # "
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command */
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/* args */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/* memtest works on */
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#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
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#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
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0x01F00000) /* 31MB */
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#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
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/* address */
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/*
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* OMAP3 has 12 GP timers, they can be driven by the system clock
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* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
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* This rate is divided by a local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
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#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
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#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
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#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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/* **** PISMO SUPPORT *** */
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/* Configure the PISMO */
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#define PISMO1_NAND_SIZE GPMC_SIZE_128M
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#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
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#if defined(CONFIG_CMD_NAND)
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#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
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#endif
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/* Monitor at start of flash */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
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#define CONFIG_ENV_IS_IN_NAND
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#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */
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#define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */
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#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
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#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
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#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
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#if defined(CONFIG_CMD_NET)
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/*----------------------------------------------------------------------------
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* SMSC9211 Ethernet from SMSC9118 family
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*----------------------------------------------------------------------------
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*/
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#define CONFIG_SMC911X
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#define CONFIG_SMC911X_32_BIT
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#define CONFIG_SMC911X_BASE 0x2C000000
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#endif /* (CONFIG_CMD_NET) */
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/*
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* Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
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* and older u-boot.bin with the new U-Boot SPL.
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*/
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#define CONFIG_SYS_TEXT_BASE 0x80008000
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
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#define CONFIG_SYS_INIT_RAM_SIZE 0x800
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_CACHELINE_SIZE 64
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/* Defines for SPL */
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#define CONFIG_SPL
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_NAND_SIMPLE
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#define CONFIG_SPL_TEXT_BASE 0x40200800
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#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
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#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
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/* move malloc and bss high to prevent clashing with the main image */
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#define CONFIG_SYS_SPL_MALLOC_START 0x87000000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
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#define CONFIG_SPL_BSS_START_ADDR 0x87080000 /* end of minimum RAM */
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
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#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
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#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
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#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
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#define CONFIG_SPL_BOARD_INIT
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBDISK_SUPPORT
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#define CONFIG_SPL_I2C_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SPL_FAT_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_NAND_BASE
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#define CONFIG_SPL_NAND_DRIVERS
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#define CONFIG_SPL_NAND_ECC
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#define CONFIG_SPL_GPIO_SUPPORT
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#define CONFIG_SPL_POWER_SUPPORT
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#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
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/* NAND boot config */
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
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#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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#endif /* __CONFIG_H */
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