mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 03:36:16 +09:00
e229d445fc
For i.MX233 addition the base registers need to be change so the SoC definition needs to be known before the header include. The following boards has been changed: * apx4devkit * m28evk * mx28evk * sc_sps_1 Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
237 lines
6.9 KiB
C
237 lines
6.9 KiB
C
/*
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* Copyright (C) 2012 Bluegiga Technologies Oy
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*
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* Authors:
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* Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
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* Lauri Hintsala <lauri.hintsala@bluegiga.com>
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*
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* Based on m28evk.h:
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* SoC configurations */
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#define CONFIG_MX28 /* i.MX28 SoC */
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#define CONFIG_MXS_GPIO /* GPIO control */
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#define CONFIG_SYS_HZ 1000 /* Ticks per second */
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#define MACH_TYPE_APX4DEVKIT 3712
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#define CONFIG_MACH_TYPE MACH_TYPE_APX4DEVKIT
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#include <asm/arch/regs-base.h>
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_ARCH_MISC_INIT
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/* SPL */
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#define CONFIG_SPL
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#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
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#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
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#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_GPIO_SUPPORT
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/* U-Boot Commands */
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#include <config_cmd_default.h>
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DOS_PARTITION
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_MMC
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SAVEENV
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#define CONFIG_CMD_USB
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/* Memory configurations */
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#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
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#define PHYS_SDRAM_1 0x40000000 /* Base address */
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#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */
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#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
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#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
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#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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/* Point initial SP in SRAM so SPL can use it too. */
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#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000
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#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024)
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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/*
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* We need to sacrifice first 4 bytes of RAM here to avoid triggering some
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* strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
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* binary. In case there was more of this mess, 0x100 bytes are skipped.
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*/
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#define CONFIG_SYS_TEXT_BASE 0x40000100
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#define CONFIG_ENV_OVERWRITE
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/* U-Boot general configurations */
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_PROMPT "=> "
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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/* Print buffer size */
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#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/* Boot argument buffer size */
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#define CONFIG_VERSION_VARIABLE /* U-Boot version */
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#define CONFIG_AUTO_COMPLETE /* Command auto complete */
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#define CONFIG_CMDLINE_EDITING /* Command history etc. */
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_OF_LIBFDT
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#define CONFIG_ENV_IS_IN_NAND
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/* Serial Driver */
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#define CONFIG_PL011_SERIAL
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#define CONFIG_PL011_CLOCK 24000000
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#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
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#define CONFIG_CONS_INDEX 0
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#define CONFIG_BAUDRATE 115200 /* Default baud rate */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/* DMA */
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#define CONFIG_APBH_DMA
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/* MMC Driver */
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#ifdef CONFIG_ENV_IS_IN_MMC
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#define CONFIG_ENV_OFFSET (256 * 1024)
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#define CONFIG_ENV_SIZE (16 * 1024)
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#endif
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#ifdef CONFIG_CMD_MMC
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_MMC_BOUNCE_BUFFER
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#define CONFIG_MXS_MMC
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#endif
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/* NAND Driver */
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#ifdef CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_SECT_SIZE (128 * 1024)
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#define CONFIG_ENV_SIZE (128 * 1024)
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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#define CONFIG_ENV_RANGE (384 * 1024)
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#define CONFIG_ENV_OFFSET 0x120000
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#define CONFIG_ENV_OFFSET_REDUND \
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(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
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#endif
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_NAND_MXS
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x60000000
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_CMD_UBI
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#define CONFIG_CMD_UBIFS
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_RBTREE
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#define CONFIG_LZO
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#define CONFIG_MTD_DEVICE
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#define CONFIG_MTD_PARTITIONS
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#define MTDIDS_DEFAULT "nand0=gpmi-nand"
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#define MTDPARTS_DEFAULT \
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"mtdparts=gpmi-nand:128k(bootstrap),1024k(boot),768k(env),-(root)"
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#else
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#define MTDPARTS_DEFAULT ""
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#endif
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/* Ethernet on SOC (FEC) */
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#ifdef CONFIG_CMD_NET
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#define CONFIG_NET_MULTI
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC
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#define CONFIG_FEC_MXC_PHYADDR 0
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#define IMX_FEC_BASE MXS_ENET0_BASE
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#define CONFIG_MII
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#define CONFIG_DISCOVER_PHY
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#define CONFIG_FEC_XCV_TYPE RMII
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#endif
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/* USB */
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#ifdef CONFIG_CMD_USB
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#define CONFIG_USB_EHCI
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#define CONFIG_USB_EHCI_MXS
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#define CONFIG_EHCI_MXS_PORT 1
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#define CONFIG_EHCI_IS_TDI
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#define CONFIG_USB_STORAGE
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#endif
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/* I2C */
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#ifdef CONFIG_CMD_I2C
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#define CONFIG_I2C_MXS
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#define CONFIG_HARD_I2C
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#define CONFIG_SYS_I2C_SPEED 400000
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#endif
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/* RTC */
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#if defined(CONFIG_CMD_DATE)
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#define CONFIG_RTC_PCF8563
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51
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#endif
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/* Boot Linux */
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_BOOTDELAY 1
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_BOOTCOMMAND "run bootcmd_nand"
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#define CONFIG_LOADADDR 0x41000000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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#define CONFIG_SERIAL_TAG
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#define CONFIG_REVISION_TAG
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/* Extra Environments */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"mtdparts=" MTDPARTS_DEFAULT "\0" \
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"verify=no\0" \
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"bootcmd=run bootcmd_nand\0" \
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"kernelargs=console=tty0 console=ttyAMA0,115200 consoleblank=0\0" \
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"bootargs_nand=" \
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"setenv bootargs ${kernelargs} ubi.mtd=3,2048 " \
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"root=ubi0:rootfs rootfstype=ubifs ${mtdparts} rw\0" \
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"bootcmd_nand=" \
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"run bootargs_nand && ubi part root 2048 && " \
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"ubifsmount rootfs && ubifsload 41000000 boot/uImage && " \
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"bootm 41000000\0" \
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"bootargs_mmc=" \
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"setenv bootargs ${kernelargs} " \
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"root=/dev/mmcblk0p2 rootwait ${mtdparts} rw\0" \
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"bootcmd_mmc=" \
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"run bootargs_mmc && mmc rescan && " \
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"ext2load mmc 0:2 41000000 boot/uImage && bootm 41000000\0" \
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""
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#endif /* __CONFIG_H */
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