mirror of
https://github.com/brain-hackers/u-boot-brain
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ea1af9f26b
On sun9i, the GTBUS manages transaction priority and bandwidth for multiple read ports when accessing DRAM. The initialisation mirrors the settings from Allwinner's boot0 for now, even though this may not be optimal for all applications (e.g. headless systems might want to give priority to IO modules). Adding a common callout to gtbus_init() from the SPL clock init with a weakly defined implementation in sunxi/clock.c to fallback to for platforms that don't require this. [wens@csie.org: Moved gtbus_sun9i.c to arch/arm/mach-sunxi/; style cleanup] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
118 lines
4.4 KiB
C
118 lines
4.4 KiB
C
/*
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* (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
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* (C) Copyright 2007-2013
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Jerry Wang <wangflord@allwinnertech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SUNXI_CPU_SUN9I_H
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#define _SUNXI_CPU_SUN9I_H
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#define REGS_AHB0_BASE 0x01C00000
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#define REGS_AHB1_BASE 0x00800000
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#define REGS_AHB2_BASE 0x03000000
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#define REGS_APB0_BASE 0x06000000
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#define REGS_APB1_BASE 0x07000000
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#define REGS_RCPUS_BASE 0x08000000
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#define SUNXI_SRAM_D_BASE 0x08100000
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/* AHB0 Module */
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#define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
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#define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
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#define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000)
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#define SUNXI_MMC0_BASE (REGS_AHB0_BASE + 0x0f000)
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#define SUNXI_MMC1_BASE (REGS_AHB0_BASE + 0x10000)
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#define SUNXI_MMC2_BASE (REGS_AHB0_BASE + 0x11000)
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#define SUNXI_MMC3_BASE (REGS_AHB0_BASE + 0x12000)
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#define SUNXI_MMC_COMMON_BASE (REGS_AHB0_BASE + 0x13000)
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#define SUNXI_SPI0_BASE (REGS_AHB0_BASE + 0x1A000)
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#define SUNXI_SPI1_BASE (REGS_AHB0_BASE + 0x1B000)
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#define SUNXI_SPI2_BASE (REGS_AHB0_BASE + 0x1C000)
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#define SUNXI_SPI3_BASE (REGS_AHB0_BASE + 0x1D000)
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#define SUNXI_GIC400_BASE (REGS_AHB0_BASE + 0x40000)
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#define SUNXI_ARMA9_GIC_BASE (REGS_AHB0_BASE + 0x41000)
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#define SUNXI_ARMA9_CPUIF_BASE (REGS_AHB0_BASE + 0x42000)
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#define SUNXI_DRAM_COM_BASE (REGS_AHB0_BASE + 0x62000)
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#define SUNXI_DRAM_CTL0_BASE (REGS_AHB0_BASE + 0x63000)
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#define SUNXI_DRAM_CTL1_BASE (REGS_AHB0_BASE + 0x64000)
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#define SUNXI_DRAM_PHY0_BASE (REGS_AHB0_BASE + 0x65000)
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#define SUNXI_DRAM_PHY1_BASE (REGS_AHB0_BASE + 0x66000)
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/* AHB1 Module */
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#define SUNXI_DMA_BASE (REGS_AHB1_BASE + 0x002000)
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#define SUNXI_USBOTG_BASE (REGS_AHB1_BASE + 0x100000)
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#define SUNXI_USBEHCI0_BASE (REGS_AHB1_BASE + 0x200000)
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#define SUNXI_USBEHCI1_BASE (REGS_AHB1_BASE + 0x201000)
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#define SUNXI_USBEHCI2_BASE (REGS_AHB1_BASE + 0x202000)
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/* AHB2 Module */
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#define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
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#define SUNXI_DISP_SYS_BASE (REGS_AHB2_BASE + 0x010000)
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#define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
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#define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
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#define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
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#define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
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#define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
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#define SUNXI_DE_BE2_BASE (REGS_AHB2_BASE + 0x280000)
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#define SUNXI_DE_DEU0_BASE (REGS_AHB2_BASE + 0x300000)
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#define SUNXI_DE_DEU1_BASE (REGS_AHB2_BASE + 0x340000)
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#define SUNXI_DE_DRC0_BASE (REGS_AHB2_BASE + 0x400000)
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#define SUNXI_DE_DRC1_BASE (REGS_AHB2_BASE + 0x440000)
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#define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
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#define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
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#define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
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#define SUNXI_MIPI_DSI0_BASE (REGS_AHB2_BASE + 0xC40000)
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/* Also seen as SUNXI_MIPI_DSI0_DPHY_BASE 0x01ca1000 */
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#define SUNXI_MIPI_DSI0_DPHY_BASE (REGS_AHB2_BASE + 0xC40100)
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#define SUNXI_HDMI_BASE (REGS_AHB2_BASE + 0xD00000)
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/* APB0 Module */
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#define SUNXI_CCM_BASE (REGS_APB0_BASE + 0x0000)
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#define SUNXI_CCMMODULE_BASE (REGS_APB0_BASE + 0x0400)
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#define SUNXI_PIO_BASE (REGS_APB0_BASE + 0x0800)
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#define SUNXI_TIMER_BASE (REGS_APB0_BASE + 0x0C00)
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#define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400)
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#define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800)
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/* APB1 Module */
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#define SUNXI_UART0_BASE (REGS_APB1_BASE + 0x0000)
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#define SUNXI_UART1_BASE (REGS_APB1_BASE + 0x0400)
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#define SUNXI_UART2_BASE (REGS_APB1_BASE + 0x0800)
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#define SUNXI_UART3_BASE (REGS_APB1_BASE + 0x0C00)
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#define SUNXI_UART4_BASE (REGS_APB1_BASE + 0x1000)
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#define SUNXI_UART5_BASE (REGS_APB1_BASE + 0x1400)
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#define SUNXI_TWI0_BASE (REGS_APB1_BASE + 0x2800)
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#define SUNXI_TWI1_BASE (REGS_APB1_BASE + 0x2C00)
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#define SUNXI_TWI2_BASE (REGS_APB1_BASE + 0x3000)
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#define SUNXI_TWI3_BASE (REGS_APB1_BASE + 0x3400)
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#define SUNXI_TWI4_BASE (REGS_APB1_BASE + 0x3800)
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/* RCPUS Module */
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#define SUNXI_PRCM_BASE (REGS_RCPUS_BASE + 0x1400)
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#define SUNXI_R_UART_BASE (REGS_RCPUS_BASE + 0x2800)
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#define SUNXI_R_PIO_BASE (REGS_RCPUS_BASE + 0x2c00)
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#define SUNXI_RSB_BASE (REGS_RCPUS_BASE + 0x3400)
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/* Misc. */
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#define SUNXI_BROM_BASE 0xFFFF0000 /* 32K */
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#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c)
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#ifndef __ASSEMBLY__
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void sunxi_board_init(void);
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void sunxi_reset(void);
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int sunxi_get_sid(unsigned int *sid);
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#endif
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#endif /* _SUNXI_CPU_SUN9I_H */
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