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![Anup Patel](/assets/img/avatar_default.png)
This patch adds SiFive UART driver. The driver is 100% DM driver and it determines input clock using clk framework. Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
216 lines
4.7 KiB
C
216 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Anup Patel <anup@brainfault.org>
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*/
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#include <clk.h>
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#include <common.h>
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#include <debug_uart.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <watchdog.h>
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#include <asm/io.h>
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#include <linux/compiler.h>
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#include <serial.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_TXFIFO_FULL 0x80000000
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#define UART_RXFIFO_EMPTY 0x80000000
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#define UART_RXFIFO_DATA 0x000000ff
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#define UART_TXCTRL_TXEN 0x1
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#define UART_RXCTRL_RXEN 0x1
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struct uart_sifive {
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u32 txfifo;
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u32 rxfifo;
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u32 txctrl;
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u32 rxctrl;
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u32 ie;
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u32 ip;
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u32 div;
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};
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struct sifive_uart_platdata {
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unsigned int clock;
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int saved_input_char;
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struct uart_sifive *regs;
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};
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/* Set up the baud rate in gd struct */
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static void _sifive_serial_setbrg(struct uart_sifive *regs,
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unsigned long clock, unsigned long baud)
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{
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writel((u32)((clock / baud) - 1), ®s->div);
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}
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static void _sifive_serial_init(struct uart_sifive *regs)
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{
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writel(UART_TXCTRL_TXEN, ®s->txctrl);
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writel(UART_RXCTRL_RXEN, ®s->rxctrl);
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writel(0, ®s->ie);
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}
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static int _sifive_serial_putc(struct uart_sifive *regs, const char c)
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{
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if (readl(®s->txfifo) & UART_TXFIFO_FULL)
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return -EAGAIN;
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writel(c, ®s->txfifo);
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return 0;
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}
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static int _sifive_serial_getc(struct uart_sifive *regs)
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{
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int ch = readl(®s->rxfifo);
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if (ch & UART_RXFIFO_EMPTY)
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return -EAGAIN;
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ch &= UART_RXFIFO_DATA;
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return (!ch) ? -EAGAIN : ch;
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}
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static int sifive_serial_setbrg(struct udevice *dev, int baudrate)
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{
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int err;
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struct clk clk;
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struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
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err = clk_get_by_index(dev, 0, &clk);
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if (!err) {
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err = clk_get_rate(&clk);
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if (!IS_ERR_VALUE(err))
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platdata->clock = err;
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} else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
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debug("SiFive UART failed to get clock\n");
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return err;
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}
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if (!platdata->clock)
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platdata->clock = dev_read_u32_default(dev, "clock-frequency", 0);
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if (!platdata->clock) {
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debug("SiFive UART clock not defined\n");
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return -EINVAL;
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}
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_sifive_serial_setbrg(platdata->regs, platdata->clock, baudrate);
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return 0;
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}
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static int sifive_serial_probe(struct udevice *dev)
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{
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struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
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/* No need to reinitialize the UART after relocation */
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if (gd->flags & GD_FLG_RELOC)
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return 0;
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platdata->saved_input_char = 0;
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_sifive_serial_init(platdata->regs);
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return 0;
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}
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static int sifive_serial_getc(struct udevice *dev)
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{
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int c;
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struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
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struct uart_sifive *regs = platdata->regs;
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if (platdata->saved_input_char > 0) {
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c = platdata->saved_input_char;
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platdata->saved_input_char = 0;
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return c;
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}
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while ((c = _sifive_serial_getc(regs)) == -EAGAIN) ;
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return c;
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}
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static int sifive_serial_putc(struct udevice *dev, const char ch)
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{
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int rc;
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struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
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while ((rc = _sifive_serial_putc(platdata->regs, ch)) == -EAGAIN) ;
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return rc;
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}
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static int sifive_serial_pending(struct udevice *dev, bool input)
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{
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struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
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struct uart_sifive *regs = platdata->regs;
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if (input) {
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if (platdata->saved_input_char > 0)
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return 1;
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platdata->saved_input_char = _sifive_serial_getc(regs);
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return (platdata->saved_input_char > 0) ? 1 : 0;
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} else {
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return !!(readl(®s->txfifo) & UART_TXFIFO_FULL);
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}
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}
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static int sifive_serial_ofdata_to_platdata(struct udevice *dev)
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{
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struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
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platdata->regs = (struct uart_sifive *)dev_read_addr(dev);
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if (IS_ERR(platdata->regs))
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return PTR_ERR(platdata->regs);
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return 0;
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}
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static const struct dm_serial_ops sifive_serial_ops = {
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.putc = sifive_serial_putc,
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.getc = sifive_serial_getc,
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.pending = sifive_serial_pending,
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.setbrg = sifive_serial_setbrg,
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};
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static const struct udevice_id sifive_serial_ids[] = {
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{ .compatible = "sifive,uart0" },
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{ }
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};
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U_BOOT_DRIVER(serial_sifive) = {
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.name = "serial_sifive",
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.id = UCLASS_SERIAL,
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.of_match = sifive_serial_ids,
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.ofdata_to_platdata = sifive_serial_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct sifive_uart_platdata),
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.probe = sifive_serial_probe,
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.ops = &sifive_serial_ops,
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};
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#ifdef CONFIG_DEBUG_UART_SIFIVE
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static inline void _debug_uart_init(void)
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{
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struct uart_sifive *regs =
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(struct uart_sifive *)CONFIG_DEBUG_UART_BASE;
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_sifive_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
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CONFIG_BAUDRATE);
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_sifive_serial_init(regs);
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}
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static inline void _debug_uart_putc(int ch)
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{
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struct uart_sifive *regs =
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(struct uart_sifive *)CONFIG_DEBUG_UART_BASE;
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while (_sifive_serial_putc(regs, ch) == -EAGAIN)
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WATCHDOG_RESET();
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}
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DEBUG_UART_FUNCS
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#endif
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