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https://github.com/brain-hackers/u-boot-brain
synced 2024-07-27 13:23:44 +09:00
ea1a7de532
This add the initial support of the broadcom bcm63158 SoC family, only the cpu, dram and uart are supported. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
86 lines
1.5 KiB
Plaintext
86 lines
1.5 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
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*/
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#include "skeleton64.dtsi"
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/ {
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compatible = "brcm,bcm63158";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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u-boot,dm-pre-reloc;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x0>;
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next-level-cache = <&l2>;
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u-boot,dm-pre-reloc;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x1>;
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next-level-cache = <&l2>;
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u-boot,dm-pre-reloc;
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x2>;
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next-level-cache = <&l2>;
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u-boot,dm-pre-reloc;
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x3>;
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next-level-cache = <&l2>;
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u-boot,dm-pre-reloc;
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};
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l2: l2-cache0 {
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compatible = "cache";
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u-boot,dm-pre-reloc;
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};
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};
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clocks {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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u-boot,dm-pre-reloc;
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periph_osc: periph-osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0xbebc200>;
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u-boot,dm-pre-reloc;
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};
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};
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ubus {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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u-boot,dm-pre-reloc;
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uart0: serial@ff812000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0xff812000 0x0 0x1000>;
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clock = <50000000>;
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status = "disabled";
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};
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};
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};
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