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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 01:48:52 +09:00
![Ye.Li](/assets/img/avatar_default.png)
The i.MX6Q/DL sabreauto board has one NAND socket, set the CONFIG_NAND_MXS and relevant NAND configurations to enable the MXS NAND flash driver. Add board level codes to set IOMUX and clock for GPMI-NAND and BCH module. Signed-off-by: Ye.Li <B37916@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
523 lines
13 KiB
C
523 lines
13 KiB
C
/*
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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*
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* Author: Fabio Estevam <fabio.estevam@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/errno.h>
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#include <asm/gpio.h>
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#include <asm/imx-common/iomux-v3.h>
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#include <asm/imx-common/mxc_i2c.h>
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#include <asm/imx-common/boot_mode.h>
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#include <asm/imx-common/spi.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/arch/sys_proto.h>
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#include <i2c.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/imx-common/video.h>
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#include <asm/arch/crm_regs.h>
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#include <pca953x.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE | PAD_CTL_SRE_FAST)
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#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
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#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
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PAD_CTL_SRE_FAST)
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#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
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return 0;
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}
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static iomux_v3_cfg_t const uart4_pads[] = {
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MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const enet_pads[] = {
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MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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};
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/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
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static struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
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.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
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.gp = IMX_GPIO_NR(2, 30)
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},
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.sda = {
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.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
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.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
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.gp = IMX_GPIO_NR(4, 13)
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}
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};
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/*
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* I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
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* Compass Sensor, Accelerometer, Res Touch
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*/
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static struct i2c_pads_info i2c_pad_info2 = {
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.scl = {
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.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
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.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
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.gp = IMX_GPIO_NR(1, 3)
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},
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.sda = {
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.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
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.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
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.gp = IMX_GPIO_NR(3, 18)
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}
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};
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static iomux_v3_cfg_t const i2c3_pads[] = {
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MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const port_exp[] = {
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MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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/*Define for building port exp gpio, pin starts from 0*/
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#define PORTEXP_IO_NR(chip, pin) \
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((chip << 5) + pin)
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/*Get the chip addr from a ioexp gpio*/
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#define PORTEXP_IO_TO_CHIP(gpio_nr) \
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(gpio_nr >> 5)
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/*Get the pin number from a ioexp gpio*/
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#define PORTEXP_IO_TO_PIN(gpio_nr) \
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(gpio_nr & 0x1f)
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static int port_exp_direction_output(unsigned gpio, int value)
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{
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int ret;
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i2c_set_bus_num(2);
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ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
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if (ret)
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return ret;
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ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
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(1 << PORTEXP_IO_TO_PIN(gpio)),
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(PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
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if (ret)
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return ret;
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ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
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(1 << PORTEXP_IO_TO_PIN(gpio)),
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(value << PORTEXP_IO_TO_PIN(gpio)));
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if (ret)
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return ret;
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return 0;
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}
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static void setup_iomux_enet(void)
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{
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imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
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}
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static iomux_v3_cfg_t const usdhc3_pads[] = {
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MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
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}
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#ifdef CONFIG_FSL_ESDHC
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static struct fsl_esdhc_cfg usdhc_cfg[1] = {
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{USDHC3_BASE_ADDR},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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gpio_direction_input(IMX_GPIO_NR(6, 15));
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return !gpio_get_value(IMX_GPIO_NR(6, 15));
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}
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int board_mmc_init(bd_t *bis)
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{
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imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
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}
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#endif
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#ifdef CONFIG_NAND_MXS
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static iomux_v3_cfg_t gpmi_pads[] = {
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MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
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MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1),
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};
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static void setup_gpmi_nand(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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/* config gpmi nand iomux */
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imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
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/* gate ENFC_CLK_ROOT clock first,before clk source switch */
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clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
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clrbits_le32(&mxc_ccm->CCGR4,
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
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/* config gpmi and bch clock to 100 MHz */
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clrsetbits_le32(&mxc_ccm->cs2cdr,
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MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
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MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
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MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
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MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
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MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
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MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
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/* enable ENFC_CLK_ROOT clock */
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setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
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/* enable gpmi and bch clock gating */
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setbits_le32(&mxc_ccm->CCGR4,
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MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
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MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
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/* enable apbh clock gating */
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setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
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}
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#endif
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int mx6_rgmii_rework(struct phy_device *phydev)
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{
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unsigned short val;
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/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
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val &= 0xffe3;
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val |= 0x18;
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
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/* introduce tx clock delay */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
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val |= 0x0100;
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
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return 0;
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}
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int board_phy_config(struct phy_device *phydev)
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{
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mx6_rgmii_rework(phydev);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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setup_iomux_enet();
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return cpu_eth_init(bis);
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}
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#define BOARD_REV_B 0x200
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#define BOARD_REV_A 0x100
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static int mx6sabre_rev(void)
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{
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/*
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* Get Board ID information from OCOTP_GP1[15:8]
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* i.MX6Q ARD RevA: 0x01
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* i.MX6Q ARD RevB: 0x02
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*/
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[4];
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struct fuse_bank4_regs *fuse =
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(struct fuse_bank4_regs *)bank->fuse_regs;
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int reg = readl(&fuse->gp1);
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int ret;
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switch (reg >> 8 & 0x0F) {
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case 0x02:
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ret = BOARD_REV_B;
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break;
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case 0x01:
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default:
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ret = BOARD_REV_A;
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break;
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}
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return ret;
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}
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u32 get_board_rev(void)
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{
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int rev = mx6sabre_rev();
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return (get_cpu_rev() & ~(0xF << 8)) | rev;
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}
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#if defined(CONFIG_VIDEO_IPUV3)
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static void do_enable_hdmi(struct display_info_t const *dev)
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{
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imx_enable_hdmi_phy();
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}
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struct display_info_t const displays[] = {{
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.bus = -1,
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.addr = 0,
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.pixfmt = IPU_PIX_FMT_RGB24,
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.detect = detect_hdmi,
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.enable = do_enable_hdmi,
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.mode = {
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.name = "HDMI",
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.refresh = 60,
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.xres = 1024,
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.yres = 768,
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.pixclock = 15385,
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.left_margin = 220,
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.right_margin = 40,
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.upper_margin = 21,
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.lower_margin = 7,
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.hsync_len = 60,
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.vsync_len = 10,
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.sync = FB_SYNC_EXT,
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.vmode = FB_VMODE_NONINTERLACED,
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} } };
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size_t display_count = ARRAY_SIZE(displays);
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static void setup_display(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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int reg;
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enable_ipu_clock();
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imx_setup_hdmi();
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reg = readl(&mxc_ccm->chsccdr);
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reg |= (CHSCCDR_CLK_SEL_LDB_DI0
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<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
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writel(reg, &mxc_ccm->chsccdr);
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}
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#endif /* CONFIG_VIDEO_IPUV3 */
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/*
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* Do not overwrite the console
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* Use always serial for U-Boot console
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*/
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int overwrite_console(void)
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{
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return 1;
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}
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int board_early_init_f(void)
|
|
{
|
|
setup_iomux_uart();
|
|
#ifdef CONFIG_VIDEO_IPUV3
|
|
setup_display();
|
|
#endif
|
|
|
|
#ifdef CONFIG_NAND_MXS
|
|
setup_gpmi_nand();
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
int board_init(void)
|
|
{
|
|
/* address of boot parameters */
|
|
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
|
|
|
/* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
|
|
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
|
/* I2C 3 Steer */
|
|
gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
|
|
imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
|
|
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
|
|
|
|
gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
|
|
imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_MXC_SPI
|
|
int board_spi_cs_gpio(unsigned bus, unsigned cs)
|
|
{
|
|
return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_CMD_BMODE
|
|
static const struct boot_mode board_boot_modes[] = {
|
|
/* 4 bit bus width */
|
|
{"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
|
|
{NULL, 0},
|
|
};
|
|
#endif
|
|
|
|
int board_late_init(void)
|
|
{
|
|
#ifdef CONFIG_CMD_BMODE
|
|
add_board_boot_modes(board_boot_modes);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
int checkboard(void)
|
|
{
|
|
int rev = mx6sabre_rev();
|
|
char *revname;
|
|
|
|
switch (rev) {
|
|
case BOARD_REV_B:
|
|
revname = "B";
|
|
break;
|
|
case BOARD_REV_A:
|
|
default:
|
|
revname = "A";
|
|
break;
|
|
}
|
|
|
|
printf("Board: MX6Q-Sabreauto rev%s\n", revname);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_USB_EHCI_MX6
|
|
#define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7)
|
|
#define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1)
|
|
|
|
iomux_v3_cfg_t const usb_otg_pads[] = {
|
|
MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
};
|
|
|
|
int board_ehci_hcd_init(int port)
|
|
{
|
|
switch (port) {
|
|
case 0:
|
|
imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
|
|
ARRAY_SIZE(usb_otg_pads));
|
|
|
|
/*
|
|
* Set daisy chain for otg_pin_id on 6q.
|
|
* For 6dl, this bit is reserved.
|
|
*/
|
|
imx_iomux_set_gpr_register(1, 13, 1, 0);
|
|
break;
|
|
case 1:
|
|
break;
|
|
default:
|
|
printf("MXC USB port %d not yet supported\n", port);
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int board_ehci_power(int port, int on)
|
|
{
|
|
switch (port) {
|
|
case 0:
|
|
if (on)
|
|
port_exp_direction_output(USB_OTG_PWR, 1);
|
|
else
|
|
port_exp_direction_output(USB_OTG_PWR, 0);
|
|
break;
|
|
case 1:
|
|
if (on)
|
|
port_exp_direction_output(USB_HOST1_PWR, 1);
|
|
else
|
|
port_exp_direction_output(USB_HOST1_PWR, 0);
|
|
break;
|
|
default:
|
|
printf("MXC USB port %d not yet supported\n", port);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|