mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 20:56:16 +09:00
e9c891ff93
The V2H Blanche port was broken since some time. This patch updates the V2H Blanche port to use modern frameworks, DM, DT probing, SPL for the preloading and puts it on par with the M2 Porter board. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
358 lines
7.6 KiB
C
358 lines
7.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* board/renesas/blanche/blanche.c
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* This file is blanche board support.
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*
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* Copyright (C) 2016 Renesas Electronics Corporation
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*/
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#include <common.h>
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#include <asm/arch/mmc.h>
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#include <asm/arch/rcar-mstp.h>
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#include <asm/arch/rmobile.h>
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#include <asm/arch/sh_sdhi.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/mach-types.h>
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#include <asm/processor.h>
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#include <dm.h>
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#include <dm/platform_data/serial_sh.h>
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#include <environment.h>
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#include <i2c.h>
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#include <linux/errno.h>
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#include <malloc.h>
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#include <miiphy.h>
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#include <mmc.h>
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#include <netdev.h>
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#include "qos.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define CPG_PLL1CR 0xE6150028
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#define CPG_PLL3CR 0xE61500DC
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#define TMU0_MSTP125 BIT(25)
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#define QSPI_MSTP917 BIT(17)
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struct reg_config {
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u16 off;
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u32 val;
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};
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static void blanche_init_sys(void)
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{
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struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
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struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
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u32 cpu_type;
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cpu_type = rmobile_get_cpu_type();
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if (cpu_type == 0x4A) {
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writel(0x4D000000, CPG_PLL1CR);
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writel(0x4F000000, CPG_PLL3CR);
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}
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/* Watchdog init */
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writel(0xA5A5A500, &rwdt->rwtcsra);
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writel(0xA5A5A500, &swdt->swtcsra);
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}
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static void blanche_init_pfc(void)
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{
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static const struct reg_config pfc_with_unlock[] = {
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{ 0x0004, 0x0bffffff },
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{ 0x0008, 0x002fffff },
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{ 0x0014, 0x00000fff },
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{ 0x0018, 0x00010fff },
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{ 0x001c, 0x00010fff },
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{ 0x0020, 0x00010fff },
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{ 0x0024, 0x00010fff },
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{ 0x0028, 0x00010fff },
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{ 0x002c, 0x04006000 },
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{ 0x0030, 0x303fefe0 },
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{ 0x0058, 0x0002000e },
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};
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static const struct reg_config pfc_without_unlock[] = {
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{ 0x0108, 0x00000000 },
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{ 0x010c, 0x0803FF40 },
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{ 0x0110, 0x0000FFFF },
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{ 0x0114, 0x00010FFF },
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{ 0x011c, 0x0001AFFF },
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{ 0x0124, 0x0001CFFF },
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{ 0x0128, 0xC0438001 },
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{ 0x012c, 0x0FC00007 },
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};
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static const u32 pfc_base = 0xe6060000;
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
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writel(~pfc_with_unlock[i].val, pfc_base);
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writel(pfc_with_unlock[i].val,
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pfc_base | pfc_with_unlock[i].off);
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}
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for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
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writel(pfc_without_unlock[i].val,
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pfc_base | pfc_without_unlock[i].off);
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}
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static void blanche_init_lbsc(void)
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{
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static const struct reg_config lbsc_config[] = {
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{ 0x00, 0x00000020 },
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{ 0x08, 0x00002020 },
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{ 0x30, 0x2a103320 },
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{ 0x38, 0x19102110 },
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};
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static const u32 lbsc_base = 0xfec00200;
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
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writel(lbsc_config[i].val,
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lbsc_base | lbsc_config[i].off);
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writel(lbsc_config[i].val,
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lbsc_base | (lbsc_config[i].off + 4));
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}
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}
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#if defined(CONFIG_MTD_NOR_FLASH)
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static void dbsc_wait(u16 reg)
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{
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static const u32 dbsc3_0_base = DBSC3_0_BASE;
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while (!(readl(dbsc3_0_base + reg) & BIT(0)))
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;
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}
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static void blanche_init_dbsc(void)
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{
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static const struct reg_config dbsc_config1[] = {
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{ 0x0280, 0x0000a55a },
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{ 0x0018, 0x21000000 },
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{ 0x0018, 0x11000000 },
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{ 0x0018, 0x10000000 },
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{ 0x0290, 0x00000001 },
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{ 0x02a0, 0x80000000 },
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{ 0x0290, 0x00000004 },
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};
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static const struct reg_config dbsc_config2[] = {
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{ 0x0290, 0x00000006 },
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{ 0x02a0, 0x0001c000 },
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};
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static const struct reg_config dbsc_config4[] = {
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{ 0x0290, 0x0000000f },
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{ 0x02a0, 0x00181ee4 },
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{ 0x0290, 0x00000010 },
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{ 0x02a0, 0xf00464db },
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{ 0x0290, 0x00000061 },
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{ 0x02a0, 0x0000008d },
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{ 0x0290, 0x00000001 },
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{ 0x02a0, 0x00000073 },
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{ 0x0020, 0x00000007 },
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{ 0x0024, 0x0f030a02 },
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{ 0x0030, 0x00000001 },
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{ 0x00b0, 0x00000000 },
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{ 0x0040, 0x0000000b },
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{ 0x0044, 0x00000008 },
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{ 0x0048, 0x00000000 },
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{ 0x0050, 0x0000000b },
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{ 0x0054, 0x000c000b },
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{ 0x0058, 0x00000027 },
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{ 0x005c, 0x0000001c },
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{ 0x0060, 0x00000006 },
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{ 0x0064, 0x00000020 },
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{ 0x0068, 0x00000008 },
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{ 0x006c, 0x0000000c },
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{ 0x0070, 0x00000009 },
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{ 0x0074, 0x00000012 },
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{ 0x0078, 0x000000d0 },
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{ 0x007c, 0x00140005 },
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{ 0x0080, 0x00050004 },
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{ 0x0084, 0x70233005 },
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{ 0x0088, 0x000c0000 },
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{ 0x008c, 0x00000300 },
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{ 0x0090, 0x00000040 },
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{ 0x0100, 0x00000001 },
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{ 0x00c0, 0x00020001 },
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{ 0x00c8, 0x20082004 },
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{ 0x0380, 0x00020002 },
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{ 0x0390, 0x0000001f },
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};
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static const struct reg_config dbsc_config5[] = {
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{ 0x0244, 0x00000011 },
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{ 0x0290, 0x00000003 },
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{ 0x02a0, 0x0300c4e1 },
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{ 0x0290, 0x00000023 },
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{ 0x02a0, 0x00fcdb60 },
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{ 0x0290, 0x00000011 },
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{ 0x02a0, 0x1000040b },
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{ 0x0290, 0x00000012 },
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{ 0x02a0, 0x9d9cbb66 },
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{ 0x0290, 0x00000013 },
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{ 0x02a0, 0x1a868400 },
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{ 0x0290, 0x00000014 },
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{ 0x02a0, 0x300214d8 },
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{ 0x0290, 0x00000015 },
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{ 0x02a0, 0x00000d70 },
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{ 0x0290, 0x00000016 },
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{ 0x02a0, 0x00000004 },
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{ 0x0290, 0x00000017 },
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{ 0x02a0, 0x00000018 },
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{ 0x0290, 0x0000001a },
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{ 0x02a0, 0x910035c7 },
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{ 0x0290, 0x00000004 },
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};
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static const struct reg_config dbsc_config6[] = {
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{ 0x0290, 0x00000001 },
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{ 0x02a0, 0x00000181 },
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{ 0x0018, 0x11000000 },
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{ 0x0290, 0x00000004 },
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};
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static const struct reg_config dbsc_config7[] = {
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{ 0x0290, 0x00000001 },
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{ 0x02a0, 0x0000fe01 },
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{ 0x0304, 0x00000000 },
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{ 0x00f4, 0x01004c20 },
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{ 0x00f8, 0x014000aa },
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{ 0x00e0, 0x00000140 },
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{ 0x00e4, 0x00081860 },
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{ 0x00e8, 0x00010000 },
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{ 0x0290, 0x00000004 },
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};
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static const struct reg_config dbsc_config8[] = {
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{ 0x0014, 0x00000001 },
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{ 0x0010, 0x00000001 },
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{ 0x0280, 0x00000000 },
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};
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static const u32 dbsc3_0_base = DBSC3_0_BASE;
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
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writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
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dbsc_wait(0x2a0);
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for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
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writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
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for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
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writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
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dbsc_wait(0x240);
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for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
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writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
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dbsc_wait(0x2a0);
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for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
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writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
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dbsc_wait(0x2a0);
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for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
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writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
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dbsc_wait(0x2a0);
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for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
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writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
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}
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static void s_init_wait(volatile unsigned int cnt)
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{
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volatile u32 i = cnt * 0x10000;
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while (i-- > 0)
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;
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}
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#endif
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void s_init(void)
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{
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blanche_init_sys();
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qos_init();
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blanche_init_pfc();
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blanche_init_lbsc();
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#if defined(CONFIG_MTD_NOR_FLASH)
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s_init_wait(10);
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blanche_init_dbsc();
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#endif /* CONFIG_MTD_NOR_FLASH */
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}
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int board_early_init_f(void)
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{
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/* TMU0 */
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mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
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/* QSPI */
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mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
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return 0;
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}
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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/* Added for BLANCHE(R-CarV2H board) */
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC911X
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struct eth_device *dev;
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uchar eth_addr[6];
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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if (!eth_env_get_enetaddr("ethaddr", eth_addr)) {
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dev = eth_get_dev_by_index(0);
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if (dev) {
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eth_env_set_enetaddr("ethaddr", dev->enetaddr);
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} else {
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printf("blanche: Couldn't get eth device\n");
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rc = -1;
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}
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}
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#endif
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return rc;
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}
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int dram_init(void)
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{
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if (fdtdec_setup_memory_size() != 0)
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return -EINVAL;
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return 0;
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}
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int dram_init_banksize(void)
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{
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fdtdec_setup_memory_banksize();
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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}
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