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![Simon Glass](/assets/img/avatar_default.png)
At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com>
170 lines
4.7 KiB
C
170 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Intel Corporation <www.intel.com>
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*
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <div64.h>
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#include <fdtdec.h>
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#include <hang.h>
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#include <ram.h>
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#include <reset.h>
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#include "sdram_soc64.h"
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#include <wait_bit.h>
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#include <asm/arch/firewall.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/system_manager.h>
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#include <asm/io.h>
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#include <linux/sizes.h>
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DECLARE_GLOBAL_DATA_PTR;
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int sdram_mmr_init_full(struct udevice *dev)
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{
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struct altera_sdram_platdata *plat = dev->platdata;
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struct altera_sdram_priv *priv = dev_get_priv(dev);
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u32 i;
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int ret;
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phys_size_t hw_size;
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bd_t bd = {0};
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/* Ensure HMC clock is running */
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if (poll_hmc_clock_status()) {
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debug("DDR: Error as HMC clock was not running\n");
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return -EPERM;
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}
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/* Trying 3 times to do a calibration */
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for (i = 0; i < 3; i++) {
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ret = wait_for_bit_le32((const void *)(plat->hmc +
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DDRCALSTAT),
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DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000,
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false);
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if (!ret)
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break;
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emif_reset(plat);
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}
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if (ret) {
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puts("DDR: Error as SDRAM calibration failed\n");
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return -EPERM;
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}
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debug("DDR: Calibration success\n");
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/*
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* Configure the DDR IO size
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* niosreserve0: Used to indicate DDR width &
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* bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit)
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* bit[8] = 1 if user-mode OCT is present
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* bit[9] = 1 if warm reset compiled into EMIF Cal Code
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* bit[10] = 1 if warm reset is on during generation in EMIF Cal
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* niosreserve1: IP ADCDS version encoded as 16 bit value
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* bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
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* 3=EAP, 4-6 are reserved)
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* bit[5:3] = Service Pack # (e.g. 1)
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* bit[9:6] = Minor Release #
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* bit[14:10] = Major Release #
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*/
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/* Configure DDR IO size x16, x32 and x64 mode */
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u32 update_value;
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update_value = hmc_readl(plat, NIOSRESERVED0);
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update_value = (update_value & 0xFF) >> 5;
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/* Configure DDR data rate 0-HAlf-rate 1-Quarter-rate */
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update_value |= (hmc_readl(plat, CTRLCFG3) & 0x4);
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hmc_ecc_writel(plat, update_value, DDRIOCTRL);
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/* Copy values MMR IOHMC dramaddrw to HMC adp DRAMADDRWIDTH */
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hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH);
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/* assigning the SDRAM size */
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phys_size_t size = sdram_calculate_size(plat);
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if (size <= 0)
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hw_size = PHYS_SDRAM_1_SIZE;
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else
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hw_size = size;
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/* Get bank configuration from devicetree */
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ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
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(phys_size_t *)&gd->ram_size, &bd);
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if (ret) {
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puts("DDR: Failed to decode memory node\n");
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return -ENXIO;
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}
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if (gd->ram_size != hw_size) {
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printf("DDR: Warning: DRAM size from device tree (%lld MiB)\n",
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gd->ram_size >> 20);
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printf(" mismatch with hardware (%lld MiB).\n",
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hw_size >> 20);
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}
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if (gd->ram_size > hw_size) {
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printf("DDR: Error: DRAM size from device tree is greater\n");
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printf(" than hardware size.\n");
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hang();
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}
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printf("DDR: %lld MiB\n", gd->ram_size >> 20);
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/* This enables nonsecure access to DDR */
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/* mpuregion0addr_limit */
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FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1,
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FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
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FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);
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/* nonmpuregion0addr_limit */
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FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1,
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FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT);
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/* Enable mpuregion0enable and nonmpuregion0enable */
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FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE,
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FW_MPU_DDR_SCR_EN_SET);
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u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1);
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/* Enable or disable the DDR ECC */
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if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
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setbits_le32(plat->hmc + ECCCTRL1,
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(DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
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DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
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DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
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clrbits_le32(plat->hmc + ECCCTRL1,
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(DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
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DDR_HMC_ECCCTL_CNT_RST_SET_MSK));
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setbits_le32(plat->hmc + ECCCTRL2,
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(DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
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DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
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setbits_le32(plat->hmc + ERRINTEN,
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DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK);
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if (!cpu_has_been_warmreset())
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sdram_init_ecc_bits(&bd);
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} else {
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clrbits_le32(plat->hmc + ECCCTRL1,
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(DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
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DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
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DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
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clrbits_le32(plat->hmc + ECCCTRL2,
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(DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
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DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
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}
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/* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC */
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writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
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sdram_size_check(&bd);
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priv->info.base = bd.bi_dram[0].start;
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priv->info.size = gd->ram_size;
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debug("DDR: HMC init success\n");
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return 0;
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}
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