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fe48d4f996
Add device table for new Micron SPI NAND devices, which have multiple dies. Also, enable support to select the dies. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
260 lines
7.2 KiB
C
260 lines
7.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2016-2017 Micron Technology, Inc.
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*
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* Authors:
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* Peter Pan <peterpandong@micron.com>
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*/
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#ifndef __UBOOT__
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#include <malloc.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#endif
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#include <linux/bitops.h>
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#include <linux/mtd/spinand.h>
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#define SPINAND_MFR_MICRON 0x2c
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#define MICRON_STATUS_ECC_MASK GENMASK(7, 4)
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#define MICRON_STATUS_ECC_NO_BITFLIPS (0 << 4)
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#define MICRON_STATUS_ECC_1TO3_BITFLIPS (1 << 4)
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#define MICRON_STATUS_ECC_4TO6_BITFLIPS (3 << 4)
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#define MICRON_STATUS_ECC_7TO8_BITFLIPS (5 << 4)
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#define MICRON_CFG_CR BIT(0)
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/*
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* As per datasheet, die selection is done by the 6th bit of Die
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* Select Register (Address 0xD0).
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*/
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#define MICRON_DIE_SELECT_REG 0xD0
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#define MICRON_SELECT_DIE(x) ((x) << 6)
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static SPINAND_OP_VARIANTS(read_cache_variants,
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SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
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static SPINAND_OP_VARIANTS(write_cache_variants,
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SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
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SPINAND_PROG_LOAD(true, 0, NULL, 0));
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static SPINAND_OP_VARIANTS(update_cache_variants,
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SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
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SPINAND_PROG_LOAD(false, 0, NULL, 0));
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static int micron_8_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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return -ERANGE;
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region->offset = mtd->oobsize / 2;
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region->length = mtd->oobsize / 2;
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return 0;
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}
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static int micron_8_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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return -ERANGE;
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/* Reserve 2 bytes for the BBM. */
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region->offset = 2;
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region->length = (mtd->oobsize / 2) - 2;
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return 0;
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}
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static const struct mtd_ooblayout_ops micron_8_ooblayout = {
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.ecc = micron_8_ooblayout_ecc,
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.rfree = micron_8_ooblayout_free,
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};
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static int micron_select_target(struct spinand_device *spinand,
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unsigned int target)
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{
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struct spi_mem_op op = SPINAND_SET_FEATURE_OP(MICRON_DIE_SELECT_REG,
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spinand->scratchbuf);
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if (target > 1)
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return -EINVAL;
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*spinand->scratchbuf = MICRON_SELECT_DIE(target);
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return spi_mem_exec_op(spinand->slave, &op);
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}
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static int micron_8_ecc_get_status(struct spinand_device *spinand,
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u8 status)
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{
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switch (status & MICRON_STATUS_ECC_MASK) {
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case STATUS_ECC_NO_BITFLIPS:
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return 0;
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case STATUS_ECC_UNCOR_ERROR:
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return -EBADMSG;
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case MICRON_STATUS_ECC_1TO3_BITFLIPS:
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return 3;
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case MICRON_STATUS_ECC_4TO6_BITFLIPS:
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return 6;
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case MICRON_STATUS_ECC_7TO8_BITFLIPS:
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return 8;
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default:
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break;
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}
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return -EINVAL;
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}
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static const struct spinand_info micron_spinand_table[] = {
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/* M79A 2Gb 3.3V */
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SPINAND_INFO("MT29F2G01ABAGD", 0x24,
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NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(µn_8_ooblayout,
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micron_8_ecc_get_status)),
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/* M79A 2Gb 1.8V */
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SPINAND_INFO("MT29F2G01ABBGD", 0x25,
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NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(µn_8_ooblayout,
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micron_8_ecc_get_status)),
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/* M78A 1Gb 3.3V */
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SPINAND_INFO("MT29F1G01ABAFD", 0x14,
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NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(µn_8_ooblayout,
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micron_8_ecc_get_status)),
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/* M78A 1Gb 1.8V */
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SPINAND_INFO("MT29F1G01ABAFD", 0x15,
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NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(µn_8_ooblayout,
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micron_8_ecc_get_status)),
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/* M79A 4Gb 3.3V */
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SPINAND_INFO("MT29F4G01ADAGD", 0x36,
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NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 2),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(µn_8_ooblayout,
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micron_8_ecc_get_status),
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SPINAND_SELECT_TARGET(micron_select_target)),
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/* M70A 4Gb 3.3V */
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SPINAND_INFO("MT29F4G01ABAFD", 0x34,
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NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_CR_FEAT_BIT,
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SPINAND_ECCINFO(µn_8_ooblayout,
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micron_8_ecc_get_status)),
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/* M70A 4Gb 1.8V */
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SPINAND_INFO("MT29F4G01ABBFD", 0x35,
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NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_CR_FEAT_BIT,
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SPINAND_ECCINFO(µn_8_ooblayout,
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micron_8_ecc_get_status)),
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/* M70A 8Gb 3.3V */
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SPINAND_INFO("MT29F8G01ADAFD", 0x46,
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NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 2),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_CR_FEAT_BIT,
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SPINAND_ECCINFO(µn_8_ooblayout,
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micron_8_ecc_get_status),
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SPINAND_SELECT_TARGET(micron_select_target)),
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/* M70A 8Gb 1.8V */
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SPINAND_INFO("MT29F8G01ADBFD", 0x47,
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NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 2),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_CR_FEAT_BIT,
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SPINAND_ECCINFO(µn_8_ooblayout,
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micron_8_ecc_get_status),
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SPINAND_SELECT_TARGET(micron_select_target)),
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};
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static int micron_spinand_detect(struct spinand_device *spinand)
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{
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u8 *id = spinand->id.data;
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int ret;
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/*
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* Micron SPI NAND read ID need a dummy byte,
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* so the first byte in raw_id is dummy.
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*/
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if (id[1] != SPINAND_MFR_MICRON)
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return 0;
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ret = spinand_match_and_init(spinand, micron_spinand_table,
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ARRAY_SIZE(micron_spinand_table), id[2]);
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if (ret)
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return ret;
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return 1;
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}
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static int micron_spinand_init(struct spinand_device *spinand)
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{
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/*
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* M70A device series enable Continuous Read feature at Power-up,
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* which is not supported. Disable this bit to avoid any possible
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* failure.
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*/
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if (spinand->flags & SPINAND_HAS_CR_FEAT_BIT)
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return spinand_upd_cfg(spinand, MICRON_CFG_CR, 0);
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return 0;
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}
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static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = {
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.detect = micron_spinand_detect,
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.init = micron_spinand_init,
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};
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const struct spinand_manufacturer micron_spinand_manufacturer = {
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.id = SPINAND_MFR_MICRON,
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.name = "Micron",
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.ops = µn_spinand_manuf_ops,
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};
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