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ddd960e6c4
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Tegra board select menu to tegra/Kconfig.
Insert the Tegra SoC select menu between the arch select and the
board select.
Architecture select
|-- Tegra Platform (Tegra)
|- Tegra SoC select (Tegra20 / 30 / 114 / 124)
|- Board select
Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="tegra*") and always "select" CONFIG_SPL as follows:
config TEGRA
bool
select SPL
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>
31 lines
824 B
C
31 lines
824 B
C
/*
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* (C) Copyright 2013
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _TEGRA124_H_
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#define _TEGRA124_H_
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#define NV_PA_SDRAM_BASE 0x80000000
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#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
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#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */
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#define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */
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#include <asm/arch-tegra/tegra.h>
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#define BCT_ODMDATA_OFFSET 1704 /* offset to ODMDATA word */
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#undef NVBOOTINFOTABLE_BCTSIZE
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#undef NVBOOTINFOTABLE_BCTPTR
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#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */
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#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */
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#define MAX_NUM_CPU 4
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#define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8)
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#define TEGRA_USB1_BASE 0x7D000000
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#endif /* _TEGRA124_H_ */
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