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https://github.com/brain-hackers/u-boot-brain
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aba11d4476
Enabling a PLL while IDDQ is high. The Linux kernel checks for this
condition and warns about it verbosely, so while this seems to work
fine, fix it up according to the programming guidelines provided in
the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup
Sequence").
Reported-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
46 lines
1009 B
C
46 lines
1009 B
C
/*
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* (C) Copyright 2010-2013
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* Tegra124 clock control definitions */
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#ifndef _TEGRA124_CLOCK_H_
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#define _TEGRA124_CLOCK_H_
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#include <asm/arch-tegra/clock.h>
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/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
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#define OSC_FREQ_SHIFT 28
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#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
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/* CLK_RST_CONTROLLER_PLLC_MISC_0 */
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#define PLLC_IDDQ (1 << 26)
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/* CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0 */
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#define SOR0_CLK_SEL0 (1 << 14)
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#define SOR0_CLK_SEL1 (1 << 15)
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int tegra_plle_enable(void);
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void clock_sor_enable_edp_clock(void);
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/**
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* clock_set_display_rate() - Set the display clock rate
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*
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* @frequency: the requested PLLD frequency
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*
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* Return the PLLD frequenc (which may not quite what was requested), or 0
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* on failure
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*/
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u32 clock_set_display_rate(u32 frequency);
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/**
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* clock_set_up_plldp() - Set up the EDP clock ready for use
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*/
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void clock_set_up_plldp(void);
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#endif /* _TEGRA124_CLOCK_H_ */
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