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https://github.com/brain-hackers/u-boot-brain
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7f1961018c
With driver model GPIOs must be requested before use. Make sure this is done correctly. (Note that the soft SPI part of universal is omitted, since this driver is about to be replaced with a driver-model-aware version) Signed-off-by: Simon Glass <sjg@chromium.org>
307 lines
6.8 KiB
C
307 lines
6.8 KiB
C
/*
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* Copyright (C) 2012 Samsung Electronics
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <fdtdec.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <i2c.h>
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#include <netdev.h>
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#include <spi.h>
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#include <asm/gpio.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/dwmmc.h>
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#include <asm/arch/mmc.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/power.h>
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#include <asm/arch/sromc.h>
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#include <power/pmic.h>
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#include <power/max77686_pmic.h>
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#include <power/tps65090_pmic.h>
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#include <tmu.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_SOUND_MAX98095
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static void board_enable_audio_codec(void)
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{
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/* Enable MAX98095 Codec */
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gpio_request(EXYNOS5_GPIO_X17, "max98095_enable");
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gpio_direction_output(EXYNOS5_GPIO_X17, 1);
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gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE);
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}
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#endif
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int exynos_init(void)
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{
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#ifdef CONFIG_SOUND_MAX98095
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board_enable_audio_codec();
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#endif
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return 0;
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}
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#if defined(CONFIG_POWER)
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#ifdef CONFIG_POWER_MAX77686
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static int pmic_reg_update(struct pmic *p, int reg, uint regval)
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{
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u32 val;
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int ret = 0;
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ret = pmic_reg_read(p, reg, &val);
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if (ret) {
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debug("%s: PMIC %d register read failed\n", __func__, reg);
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return -1;
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}
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val |= regval;
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ret = pmic_reg_write(p, reg, val);
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if (ret) {
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debug("%s: PMIC %d register write failed\n", __func__, reg);
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return -1;
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}
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return 0;
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}
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static int max77686_init(void)
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{
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struct pmic *p;
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if (pmic_init(I2C_PMIC))
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return -1;
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p = pmic_get("MAX77686_PMIC");
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if (!p)
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return -ENODEV;
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if (pmic_probe(p))
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return -1;
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if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
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return -1;
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if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
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MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
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return -1;
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/* VDD_MIF */
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if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
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MAX77686_BUCK1OUT_1V)) {
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debug("%s: PMIC %d register write failed\n", __func__,
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MAX77686_REG_PMIC_BUCK1OUT);
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return -1;
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}
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if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
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MAX77686_BUCK1CTRL_EN))
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return -1;
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/* VDD_ARM */
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if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
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MAX77686_BUCK2DVS1_1_3V)) {
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debug("%s: PMIC %d register write failed\n", __func__,
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MAX77686_REG_PMIC_BUCK2DVS1);
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return -1;
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}
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if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
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MAX77686_BUCK2CTRL_ON))
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return -1;
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/* VDD_INT */
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if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
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MAX77686_BUCK3DVS1_1_0125V)) {
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debug("%s: PMIC %d register write failed\n", __func__,
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MAX77686_REG_PMIC_BUCK3DVS1);
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return -1;
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}
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if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
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MAX77686_BUCK3CTRL_ON))
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return -1;
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/* VDD_G3D */
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if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
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MAX77686_BUCK4DVS1_1_2V)) {
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debug("%s: PMIC %d register write failed\n", __func__,
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MAX77686_REG_PMIC_BUCK4DVS1);
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return -1;
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}
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if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
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MAX77686_BUCK3CTRL_ON))
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return -1;
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/* VDD_LDO2 */
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if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
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MAX77686_LD02CTRL1_1_5V | EN_LDO))
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return -1;
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/* VDD_LDO3 */
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if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
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MAX77686_LD03CTRL1_1_8V | EN_LDO))
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return -1;
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/* VDD_LDO5 */
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if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
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MAX77686_LD05CTRL1_1_8V | EN_LDO))
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return -1;
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/* VDD_LDO10 */
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if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
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MAX77686_LD10CTRL1_1_8V | EN_LDO))
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return -1;
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return 0;
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}
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#endif /* CONFIG_POWER_MAX77686 */
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int exynos_power_init(void)
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{
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int ret = 0;
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#ifdef CONFIG_POWER_MAX77686
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ret = max77686_init();
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if (ret)
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return ret;
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#endif
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#ifdef CONFIG_POWER_TPS65090
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/*
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* The TPS65090 may not be in the device tree. If so, it is not
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* an error.
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*/
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ret = tps65090_init();
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if (ret == 0 || ret == -ENODEV)
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return 0;
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#endif
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return ret;
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}
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#endif /* CONFIG_POWER */
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#ifdef CONFIG_LCD
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static int board_dp_bridge_setup(void)
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{
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const int max_tries = 10;
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int num_tries, node;
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/*
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* TODO(sjg): Use device tree for GPIOs when exynos GPIO
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* numbering patch is in mainline.
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*/
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debug("%s\n", __func__);
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node = fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_NXP_PTN3460);
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if (node < 0) {
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debug("%s: No node for DP bridge in device tree\n", __func__);
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return -ENODEV;
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}
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/* Setup the GPIOs */
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/* PD is ACTIVE_LOW, and initially de-asserted */
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gpio_request(EXYNOS5_GPIO_Y25, "dp_bridge_pd");
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gpio_set_pull(EXYNOS5_GPIO_Y25, S5P_GPIO_PULL_NONE);
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gpio_direction_output(EXYNOS5_GPIO_Y25, 1);
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/* Reset is ACTIVE_LOW */
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gpio_request(EXYNOS5_GPIO_X15, "dp_bridge_reset");
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gpio_set_pull(EXYNOS5_GPIO_X15, S5P_GPIO_PULL_NONE);
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gpio_direction_output(EXYNOS5_GPIO_X15, 0);
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udelay(10);
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gpio_set_value(EXYNOS5_GPIO_X15, 1);
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gpio_request(EXYNOS5_GPIO_X07, "dp_bridge_hpd");
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gpio_direction_input(EXYNOS5_GPIO_X07);
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/*
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* We need to wait for 90ms after bringing up the bridge since there
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* is a phantom "high" on the HPD chip during its bootup. The phantom
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* high comes within 7ms of de-asserting PD and persists for at least
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* 15ms. The real high comes roughly 50ms after PD is de-asserted. The
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* phantom high makes it hard for us to know when the NXP chip is up.
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*/
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mdelay(90);
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for (num_tries = 0; num_tries < max_tries; num_tries++) {
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/* Check HPD. If it's high, we're all good. */
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if (gpio_get_value(EXYNOS5_GPIO_X07))
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return 0;
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debug("%s: eDP bridge failed to come up; try %d of %d\n",
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__func__, num_tries, max_tries);
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}
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/* Immediately go into bridge reset if the hp line is not high */
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return -ENODEV;
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}
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void exynos_cfg_lcd_gpio(void)
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{
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/* For Backlight */
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gpio_request(EXYNOS5_GPIO_B20, "lcd_backlight");
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gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT);
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gpio_set_value(EXYNOS5_GPIO_B20, 1);
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/* LCD power on */
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gpio_request(EXYNOS5_GPIO_X15, "lcd_power");
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gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT);
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gpio_set_value(EXYNOS5_GPIO_X15, 1);
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/* Set Hotplug detect for DP */
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gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3));
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}
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void exynos_set_dp_phy(unsigned int onoff)
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{
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set_dp_phy_ctrl(onoff);
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}
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void exynos_backlight_on(unsigned int on)
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{
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debug("%s(%u)\n", __func__, on);
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if (!on)
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return;
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#ifdef CONFIG_POWER_TPS65090
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int ret;
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ret = tps65090_fet_enable(1); /* Enable FET1, backlight */
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if (ret)
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return;
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/* T5 in the LCD timing spec (defined as > 10ms) */
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mdelay(10);
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/* board_dp_backlight_pwm */
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gpio_direction_output(EXYNOS5_GPIO_B20, 1);
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/* T6 in the LCD timing spec (defined as > 10ms) */
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mdelay(10);
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/* board_dp_backlight_en */
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gpio_request(EXYNOS5_GPIO_X30, "board_dp_backlight_en");
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gpio_direction_output(EXYNOS5_GPIO_X30, 1);
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#endif
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}
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void exynos_lcd_power_on(void)
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{
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int ret;
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debug("%s\n", __func__);
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#ifdef CONFIG_POWER_TPS65090
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/* board_dp_lcd_vdd */
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tps65090_fet_enable(6); /* Enable FET6, lcd panel */
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#endif
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ret = board_dp_bridge_setup();
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if (ret && ret != -ENODEV)
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printf("LCD bridge failed to enable: %d\n", ret);
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}
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#endif
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