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https://github.com/brain-hackers/u-boot-brain
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db544b9662
Commit 3ff46cc4 fixed exception vectors setting in
the general ARM case, by either copying the exception
and indirect vector tables to normal (0x00000000) or
high (0xFFFF0000) vectors address, or setting VBAR to
U-Boot's base if applicable.
i.MX27 SoC is ARM926E-JS, thus has only normal and
high options, but does not provide RAM at 0xFFFF0000
and has only ROM at 0x00000000; it is therefore not
possible to move or change its exception vectors.
Besides, i.MX27 ROM code does provide an indirect
vectors table but at a non-standard address and with
the reset and reserved vectors missing.
Turn the current vector relocation code into a weak
routine called after relocate_code from crt0, and add
strong version for i.MX27.
Series-Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Tested-by: Stefano Babic <sbabic@denx.de>
Tested-by: Philippe Reynes <tremyfr@gmail.com>
Tested-by: Philippe Reynes <tremyfr@yahoo.fr>
118 lines
3.0 KiB
ArmAsm
118 lines
3.0 KiB
ArmAsm
/*
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* relocate - common relocation function for ARM U-Boot
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*
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* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <linux/linkage.h>
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/*
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* Default/weak exception vectors relocation routine
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*
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* This routine covers the standard ARM cases: normal (0x00000000),
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* high (0xffff0000) and VBAR. SoCs which do not comply with any of
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* the standard cases must provide their own, strong, version.
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*/
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.section .text.relocate_vectors,"ax",%progbits
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.weak relocate_vectors
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ENTRY(relocate_vectors)
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#ifdef CONFIG_HAS_VBAR
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/*
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* If the ARM processor has the security extensions,
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* use VBAR to relocate the exception vectors.
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*/
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ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
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mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */
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#else
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/*
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* Copy the relocated exception vectors to the
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* correct address
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* CP15 c1 V bit gives us the location of the vectors:
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* 0x00000000 or 0xFFFF0000.
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*/
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ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
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mrc p15, 0, r2, c1, c0, 0 /* V bit (bit[13]) in CP15 c1 */
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ands r2, r2, #(1 << 13)
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ldreq r1, =0x00000000 /* If V=0 */
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ldrne r1, =0xFFFF0000 /* If V=1 */
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ldmia r0!, {r2-r8,r10}
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stmia r1!, {r2-r8,r10}
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ldmia r0!, {r2-r8,r10}
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stmia r1!, {r2-r8,r10}
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#endif
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bx lr
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ENDPROC(relocate_vectors)
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/*
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* void relocate_code(addr_moni)
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*
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* This function relocates the monitor code.
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*
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* NOTE:
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* To prevent the code below from containing references with an R_ARM_ABS32
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* relocation record type, we never refer to linker-defined symbols directly.
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* Instead, we declare literals which contain their relative location with
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* respect to relocate_code, and at run time, add relocate_code back to them.
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*/
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ENTRY(relocate_code)
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ldr r1, =__image_copy_start /* r1 <- SRC &__image_copy_start */
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subs r4, r0, r1 /* r4 <- relocation offset */
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beq relocate_done /* skip relocation */
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ldr r2, =__image_copy_end /* r2 <- SRC &__image_copy_end */
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copy_loop:
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ldmia r1!, {r10-r11} /* copy from source address [r1] */
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stmia r0!, {r10-r11} /* copy to target address [r0] */
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cmp r1, r2 /* until source end address [r2] */
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blo copy_loop
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/*
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* fix .rel.dyn relocations
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*/
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ldr r2, =__rel_dyn_start /* r2 <- SRC &__rel_dyn_start */
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ldr r3, =__rel_dyn_end /* r3 <- SRC &__rel_dyn_end */
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fixloop:
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ldmia r2!, {r0-r1} /* (r0,r1) <- (SRC location,fixup) */
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and r1, r1, #0xff
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cmp r1, #23 /* relative fixup? */
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bne fixnext
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/* relative fix: increase location by offset */
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add r0, r0, r4
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ldr r1, [r0]
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add r1, r1, r4
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str r1, [r0]
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fixnext:
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cmp r2, r3
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blo fixloop
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relocate_done:
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#ifdef __XSCALE__
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/*
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* On xscale, icache must be invalidated and write buffers drained,
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* even with cache disabled - 4.2.7 of xscale core developer's manual
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*/
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mcr p15, 0, r0, c7, c7, 0 /* invalidate icache */
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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#endif
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/* ARMv4- don't know bx lr but the assembler fails to see that */
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#ifdef __ARM_ARCH_4__
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mov pc, lr
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#else
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bx lr
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#endif
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ENDPROC(relocate_code)
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