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656e6cc86b
Add a DM port of Marvell pin control driver. The A8K SoC family contains several silicone dies interconnected in a single package. Every die is normally equipped with its own pin controller unit. There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
32 lines
736 B
C
32 lines
736 B
C
/*
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* Copyright (C) 2016 Marvell International Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0
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* https://spdx.org/licenses
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*/
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#ifndef __PINCTRL_MVEBU_H_
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#define __PINCTRL_MVEBU_H_
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#define MVEBU_MAX_PINCTL_BANKS 4
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#define MVEBU_MAX_PINS_PER_BANK 100
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#define MVEBU_MAX_FUNC 0xF
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/*
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* struct mvebu_pin_bank_data: mvebu-pinctrl bank data
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* @base_reg: controller base address for this bank
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* @pin_cnt: number of pins included in this bank
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* @max_func: maximum configurable function value for pins in this bank
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* @reg_direction:
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* @bank_name: the pin's bank name
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*/
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struct mvebu_pinctrl_priv {
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void *base_reg;
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uint pin_cnt;
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uint max_func;
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int reg_direction;
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const char *bank_name;
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};
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#endif /* __PINCTRL_MVEBU_H_ */
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