mirror of
https://github.com/brain-hackers/u-boot-brain
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112 lines
2.3 KiB
Plaintext
112 lines
2.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR MIT
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/*
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* sama7g5ek.dts - Device Tree file for SAMA7G5 EK
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* SAMA7G5 Evaluation Kit
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*
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* Copyright (c) 2020, Microchip Technology Inc.
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* 2020, Eugen Hristev <eugen.hristev@microchip.com>
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* 2020, Claudiu Beznea <claudiu.beznea@microchip.com>
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*/
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/dts-v1/;
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#include "sama7g5.dtsi"
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#include "sama7g5-pinfunc.h"
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/ {
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model = "Microchip SAMA7G5 Evaluation Kit";
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compatible = "microchip,sama7g5ek", "microchip,sama7g54", "microchip,sama7g5", "microchip,sama7";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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clocks {
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slow_xtal: slow_xtal {
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clock-frequency = <32768>;
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};
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main_xtal: main_xtal {
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clock-frequency = <24000000>;
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};
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};
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ahb {
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apb {
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sdmmc1: sdio-host@e1208000 {
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bus-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sdmmc1_cmd_data_default
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&pinctrl_sdmmc1_ck_cd_rstn_vddsel_default>;
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status = "okay";
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};
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uart0: serial@e1824200 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flx3_default>;
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status = "okay";
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};
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};
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};
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};
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&gmac0 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gmac0_default>;
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phy-mode = "rgmii-id";
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status = "okay";
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ethernet-phy@7 {
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reg = <0x7>;
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};
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};
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&pinctrl {
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pinctrl_flx3_default: flx3_default {
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pinmux = <PIN_PD16__FLEXCOM3_IO0>,
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<PIN_PD17__FLEXCOM3_IO1>;
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bias-disable;
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};
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pinctrl_sdmmc1_cmd_data_default: sdmmc1_cmd_data_default {
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pinmux = <PIN_PB29__SDMMC1_CMD>,
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<PIN_PB31__SDMMC1_DAT0>,
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<PIN_PC0__SDMMC1_DAT1>,
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<PIN_PC1__SDMMC1_DAT2>,
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<PIN_PC2__SDMMC1_DAT3>;
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bias-pull-up;
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};
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pinctrl_sdmmc1_ck_cd_rstn_vddsel_default: sdmmc1_ck_cd_rstn_vddsel_default {
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pinmux = <PIN_PB30__SDMMC1_CK>,
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<PIN_PB28__SDMMC1_RSTN>,
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<PIN_PC5__SDMMC1_1V8SEL>,
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<PIN_PC4__SDMMC1_CD>;
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bias-pull-up;
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};
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pinctrl_gmac0_default: gmac0_default {
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pinmux = <PIN_PA16__G0_TX0>,
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<PIN_PA17__G0_TX1>,
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<PIN_PA26__G0_TX2>,
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<PIN_PA27__G0_TX3>,
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<PIN_PA19__G0_RX0>,
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<PIN_PA20__G0_RX1>,
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<PIN_PA28__G0_RX2>,
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<PIN_PA29__G0_RX3>,
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<PIN_PA15__G0_TXEN>,
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<PIN_PA24__G0_TXCK>,
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<PIN_PA30__G0_RXCK>,
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<PIN_PA18__G0_RXDV>,
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<PIN_PA22__G0_MDC>,
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<PIN_PA23__G0_MDIO>,
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<PIN_PA25__G0_125CK>;
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bias-disable;
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};
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};
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