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https://github.com/brain-hackers/u-boot-brain
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e945816efb
Add initial clock driver for Allwinner H3/H5. - Implement USB bus and USB clocks via ccu_clk_gate table for H3/H5, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for H3/H5, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
80 lines
2.3 KiB
C
80 lines
2.3 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2018 Amarula Solutions.
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/arch/ccu.h>
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#include <dt-bindings/clock/sun8i-h3-ccu.h>
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#include <dt-bindings/reset/sun8i-h3-ccu.h>
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static struct ccu_clk_gate h3_gates[] = {
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[CLK_BUS_OTG] = GATE(0x060, BIT(23)),
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[CLK_BUS_EHCI0] = GATE(0x060, BIT(24)),
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[CLK_BUS_EHCI1] = GATE(0x060, BIT(25)),
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[CLK_BUS_EHCI2] = GATE(0x060, BIT(26)),
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[CLK_BUS_EHCI3] = GATE(0x060, BIT(27)),
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[CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
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[CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),
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[CLK_BUS_OHCI2] = GATE(0x060, BIT(30)),
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[CLK_BUS_OHCI3] = GATE(0x060, BIT(31)),
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[CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
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[CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
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[CLK_USB_PHY2] = GATE(0x0cc, BIT(10)),
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[CLK_USB_PHY3] = GATE(0x0cc, BIT(11)),
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[CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
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[CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
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[CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)),
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[CLK_USB_OHCI3] = GATE(0x0cc, BIT(19)),
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};
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static struct ccu_reset h3_resets[] = {
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[RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
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[RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
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[RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
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[RST_USB_PHY3] = RESET(0x0cc, BIT(3)),
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[RST_BUS_OTG] = RESET(0x2c0, BIT(23)),
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[RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)),
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[RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)),
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[RST_BUS_EHCI2] = RESET(0x2c0, BIT(26)),
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[RST_BUS_EHCI3] = RESET(0x2c0, BIT(27)),
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[RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)),
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[RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),
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[RST_BUS_OHCI2] = RESET(0x2c0, BIT(30)),
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[RST_BUS_OHCI3] = RESET(0x2c0, BIT(31)),
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};
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static const struct ccu_desc h3_ccu_desc = {
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.gates = h3_gates,
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.resets = h3_resets,
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};
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static int h3_clk_bind(struct udevice *dev)
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{
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return sunxi_reset_bind(dev, ARRAY_SIZE(h3_resets));
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}
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static const struct udevice_id h3_ccu_ids[] = {
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{ .compatible = "allwinner,sun8i-h3-ccu",
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.data = (ulong)&h3_ccu_desc },
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{ .compatible = "allwinner,sun50i-h5-ccu",
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.data = (ulong)&h3_ccu_desc },
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{ }
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};
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U_BOOT_DRIVER(clk_sun8i_h3) = {
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.name = "sun8i_h3_ccu",
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.id = UCLASS_CLK,
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.of_match = h3_ccu_ids,
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.priv_auto_alloc_size = sizeof(struct ccu_priv),
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.ops = &sunxi_clk_ops,
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.probe = sunxi_clk_probe,
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.bind = h3_clk_bind,
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};
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