mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-29 05:18:51 +09:00
![]() The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
||
---|---|---|
.. | ||
arm | ||
avr32 | ||
blackfin | ||
i386 | ||
m68k | ||
microblaze | ||
mips | ||
nios2 | ||
powerpc | ||
sh | ||
sparc | ||
.gitignore |