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https://github.com/brain-hackers/u-boot-brain
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e935409199
The MODEMR register offset changed on R8A779A0, make the MODEMR offset configurable. Fill the offset in on all clock drivers. No functional change. Based off "clk: renesas: Make CPG Reset MODEMR offset accessible from struct cpg_mssr_info" by Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
122 lines
3.5 KiB
C
122 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Renesas RCar Gen3 CPG MSSR driver
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*
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* Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
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*
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* Based on the following driver from Linux kernel:
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* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2016 Glider bvba
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*/
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#ifndef __DRIVERS_CLK_RENESAS_CPG_MSSR__
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#define __DRIVERS_CLK_RENESAS_CPG_MSSR__
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#include <linux/bitops.h>
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struct cpg_mssr_info {
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const struct cpg_core_clk *core_clk;
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unsigned int core_clk_size;
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const struct mssr_mod_clk *mod_clk;
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unsigned int mod_clk_size;
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const struct mstp_stop_table *mstp_table;
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unsigned int mstp_table_size;
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const char *reset_node;
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unsigned int reset_modemr_offset;
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const char *extalr_node;
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const char *extal_usb_node;
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unsigned int mod_clk_base;
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unsigned int clk_extal_id;
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unsigned int clk_extalr_id;
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unsigned int clk_extal_usb_id;
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unsigned int pll0_div;
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const void *(*get_pll_config)(const u32 cpg_mode);
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};
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/*
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* Definitions of CPG Core Clocks
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*
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* These include:
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* - Clock outputs exported to DT
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* - External input clocks
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* - Internal CPG clocks
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*/
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struct cpg_core_clk {
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/* Common */
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const char *name;
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unsigned int id;
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unsigned int type;
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/* Depending on type */
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unsigned int parent; /* Core Clocks only */
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unsigned int div;
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unsigned int mult;
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unsigned int offset;
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};
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enum clk_types {
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/* Generic */
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CLK_TYPE_IN, /* External Clock Input */
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CLK_TYPE_FF, /* Fixed Factor Clock */
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CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
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CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
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CLK_TYPE_FR, /* Fixed Rate Clock */
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/* Custom definitions start here */
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CLK_TYPE_CUSTOM,
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};
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#define DEF_TYPE(_name, _id, _type...) \
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{ .name = _name, .id = _id, .type = _type }
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#define DEF_BASE(_name, _id, _type, _parent...) \
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DEF_TYPE(_name, _id, _type, .parent = _parent)
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#define DEF_INPUT(_name, _id) \
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DEF_TYPE(_name, _id, CLK_TYPE_IN)
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#define DEF_FIXED(_name, _id, _parent, _div, _mult) \
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DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
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#define DEF_DIV6P1(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
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#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
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DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
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#define DEF_RATE(_name, _id, _rate) \
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DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)
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/*
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* Definitions of Module Clocks
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*/
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struct mssr_mod_clk {
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const char *name;
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unsigned int id;
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unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */
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};
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/* Convert from sparse base-100 to packed index space */
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#define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
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#define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x))
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#define DEF_MOD(_name, _mod, _parent...) \
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{ .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
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struct mstp_stop_table {
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u32 sdis;
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u32 sen;
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u32 rdis;
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u32 ren;
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};
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#define TSTR0 0x04
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#define TSTR0_STR0 BIT(0)
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bool renesas_clk_is_mod(struct clk *clk);
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int renesas_clk_get_mod(struct clk *clk, struct cpg_mssr_info *info,
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const struct mssr_mod_clk **mssr);
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int renesas_clk_get_core(struct clk *clk, struct cpg_mssr_info *info,
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const struct cpg_core_clk **core);
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int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
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struct clk *parent);
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int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable);
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int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info);
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#endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */
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