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https://github.com/brain-hackers/u-boot-brain
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e92e580350
With the RK3399 DRAM controller (DMC) driver providing all the infrastructure, retrieve the DRAM size from the DMC init in the board-specific code (instead of hard-coding) for the RK3399-Q7 (Puma). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
96 lines
2.0 KiB
C
96 lines
2.0 KiB
C
/*
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* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <misc.h>
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#include <ram.h>
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#include <dm/pinctrl.h>
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#include <dm/uclass-internal.h>
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#include <asm/arch/periph.h>
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#include <power/regulator.h>
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#include <u-boot/sha256.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define RK3399_CPUID_OFF 0x7
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#define RK3399_CPUID_LEN 0x10
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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struct udevice *pinctrl, *regulator;
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int ret;
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/*
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* The PWM does not have decicated interrupt number in dts and can
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* not get periph_id by pinctrl framework, so let's init them here.
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* The PWM2 and PWM3 are for pwm regulators.
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*/
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ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
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if (ret) {
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debug("%s: Cannot find pinctrl device\n", __func__);
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goto out;
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}
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ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM2);
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if (ret) {
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debug("%s PWM2 pinctrl init fail!\n", __func__);
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goto out;
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}
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/* rk3399 need to init vdd_center to get the correct output voltage */
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ret = regulator_get_by_platname("vdd_center", ®ulator);
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if (ret)
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debug("%s: Cannot get vdd_center regulator\n", __func__);
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ret = regulator_get_by_platname("vcc5v0_host", ®ulator);
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if (ret) {
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debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret);
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goto out;
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}
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ret = regulator_set_enable(regulator, true);
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if (ret) {
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debug("%s vcc5v0-host-en set fail!\n", __func__);
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goto out;
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}
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out:
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return 0;
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}
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int dram_init(void)
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{
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struct ram_info ram;
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struct udevice *dev;
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int ret;
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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debug("DRAM init failed: %d\n", ret);
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return ret;
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}
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ret = ram_get_info(dev, &ram);
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if (ret) {
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debug("Cannot get DRAM size: %d\n", ret);
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return ret;
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}
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debug("SDRAM base=%llx, size=%x\n", ram.base, (unsigned int)ram.size);
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gd->ram_size = ram.size;
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return 0;
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}
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int dram_init_banksize(void)
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{
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/* Reserve 0x200000 for ATF bl31 */
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gd->bd->bi_dram[0].start = 0x200000;
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gd->bd->bi_dram[0].size = 0x7e000000;
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return 0;
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}
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