mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
184 lines
4.7 KiB
C
184 lines
4.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2009
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*/
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#ifndef __DW_UDC_H
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#define __DW_UDC_H
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/*
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* Defines for USBD
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*
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* The udc_ahb controller has three AHB slaves:
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*
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* 1. THe UDC registers
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* 2. The plug detect
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* 3. The RX/TX FIFO
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*/
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#define MAX_ENDPOINTS 16
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struct udc_endp_regs {
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u32 endp_cntl;
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u32 endp_status;
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u32 endp_bsorfn;
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u32 endp_maxpacksize;
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u32 reserved_1;
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u32 endp_desc_point;
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u32 reserved_2;
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u32 write_done;
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};
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/* Endpoint Control Register definitions */
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#define ENDP_CNTL_STALL 0x00000001
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#define ENDP_CNTL_FLUSH 0x00000002
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#define ENDP_CNTL_SNOOP 0x00000004
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#define ENDP_CNTL_POLL 0x00000008
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#define ENDP_CNTL_CONTROL 0x00000000
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#define ENDP_CNTL_ISO 0x00000010
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#define ENDP_CNTL_BULK 0x00000020
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#define ENDP_CNTL_INT 0x00000030
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#define ENDP_CNTL_NAK 0x00000040
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#define ENDP_CNTL_SNAK 0x00000080
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#define ENDP_CNTL_CNAK 0x00000100
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#define ENDP_CNTL_RRDY 0x00000200
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/* Endpoint Satus Register definitions */
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#define ENDP_STATUS_PIDMSK 0x0000000f
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#define ENDP_STATUS_OUTMSK 0x00000030
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#define ENDP_STATUS_OUT_NONE 0x00000000
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#define ENDP_STATUS_OUT_DATA 0x00000010
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#define ENDP_STATUS_OUT_SETUP 0x00000020
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#define ENDP_STATUS_IN 0x00000040
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#define ENDP_STATUS_BUFFNAV 0x00000080
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#define ENDP_STATUS_FATERR 0x00000100
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#define ENDP_STATUS_HOSTBUSERR 0x00000200
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#define ENDP_STATUS_TDC 0x00000400
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#define ENDP_STATUS_RXPKTMSK 0x003ff800
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struct udc_regs {
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struct udc_endp_regs in_regs[MAX_ENDPOINTS];
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struct udc_endp_regs out_regs[MAX_ENDPOINTS];
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u32 dev_conf;
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u32 dev_cntl;
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u32 dev_stat;
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u32 dev_int;
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u32 dev_int_mask;
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u32 endp_int;
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u32 endp_int_mask;
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u32 reserved_3[0x39];
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u32 reserved_4; /* offset 0x500 */
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u32 udc_endp_reg[MAX_ENDPOINTS];
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};
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/* Device Configuration Register definitions */
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#define DEV_CONF_HS_SPEED 0x00000000
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#define DEV_CONF_LS_SPEED 0x00000002
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#define DEV_CONF_FS_SPEED 0x00000003
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#define DEV_CONF_REMWAKEUP 0x00000004
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#define DEV_CONF_SELFPOW 0x00000008
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#define DEV_CONF_SYNCFRAME 0x00000010
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#define DEV_CONF_PHYINT_8 0x00000020
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#define DEV_CONF_PHYINT_16 0x00000000
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#define DEV_CONF_UTMI_BIDIR 0x00000040
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#define DEV_CONF_STATUS_STALL 0x00000080
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/* Device Control Register definitions */
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#define DEV_CNTL_RESUME 0x00000001
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#define DEV_CNTL_TFFLUSH 0x00000002
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#define DEV_CNTL_RXDMAEN 0x00000004
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#define DEV_CNTL_TXDMAEN 0x00000008
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#define DEV_CNTL_DESCRUPD 0x00000010
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#define DEV_CNTL_BIGEND 0x00000020
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#define DEV_CNTL_BUFFILL 0x00000040
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#define DEV_CNTL_TSHLDEN 0x00000080
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#define DEV_CNTL_BURSTEN 0x00000100
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#define DEV_CNTL_DMAMODE 0x00000200
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#define DEV_CNTL_SOFTDISCONNECT 0x00000400
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#define DEV_CNTL_SCALEDOWN 0x00000800
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#define DEV_CNTL_BURSTLENU 0x00010000
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#define DEV_CNTL_BURSTLENMSK 0x00ff0000
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#define DEV_CNTL_TSHLDLENU 0x01000000
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#define DEV_CNTL_TSHLDLENMSK 0xff000000
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/* Device Status Register definitions */
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#define DEV_STAT_CFG 0x0000000f
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#define DEV_STAT_INTF 0x000000f0
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#define DEV_STAT_ALT 0x00000f00
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#define DEV_STAT_SUSP 0x00001000
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#define DEV_STAT_ENUM 0x00006000
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#define DEV_STAT_ENUM_SPEED_HS 0x00000000
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#define DEV_STAT_ENUM_SPEED_FS 0x00002000
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#define DEV_STAT_ENUM_SPEED_LS 0x00004000
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#define DEV_STAT_RXFIFO_EMPTY 0x00008000
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#define DEV_STAT_PHY_ERR 0x00010000
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#define DEV_STAT_TS 0xf0000000
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/* Device Interrupt Register definitions */
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#define DEV_INT_MSK 0x0000007f
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#define DEV_INT_SETCFG 0x00000001
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#define DEV_INT_SETINTF 0x00000002
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#define DEV_INT_INACTIVE 0x00000004
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#define DEV_INT_USBRESET 0x00000008
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#define DEV_INT_SUSPUSB 0x00000010
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#define DEV_INT_SOF 0x00000020
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#define DEV_INT_ENUM 0x00000040
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/* Endpoint Interrupt Register definitions */
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#define ENDP0_INT_CTRLIN 0x00000001
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#define ENDP1_INT_BULKIN 0x00000002
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#define ENDP_INT_NONISOIN_MSK 0x0000AAAA
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#define ENDP2_INT_BULKIN 0x00000004
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#define ENDP0_INT_CTRLOUT 0x00010000
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#define ENDP1_INT_BULKOUT 0x00020000
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#define ENDP2_INT_BULKOUT 0x00040000
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#define ENDP_INT_NONISOOUT_MSK 0x55540000
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/* Endpoint Register definitions */
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#define ENDP_EPDIR_OUT 0x00000000
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#define ENDP_EPDIR_IN 0x00000010
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#define ENDP_EPTYPE_CNTL 0x0
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#define ENDP_EPTYPE_ISO 0x1
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#define ENDP_EPTYPE_BULK 0x2
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#define ENDP_EPTYPE_INT 0x3
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/*
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* Defines for Plug Detect
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*/
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struct plug_regs {
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u32 plug_state;
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u32 plug_pending;
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};
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/* Plug State Register definitions */
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#define PLUG_STATUS_EN 0x1
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#define PLUG_STATUS_ATTACHED 0x2
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#define PLUG_STATUS_PHY_RESET 0x4
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#define PLUG_STATUS_PHY_MODE 0x8
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/*
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* Defines for UDC FIFO (Slave Mode)
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*/
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struct udcfifo_regs {
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u32 *fifo_p;
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};
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/*
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* UDC endpoint definitions
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*/
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#define UDC_EP0 0
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#define UDC_EP1 1
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#define UDC_EP2 2
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#define UDC_EP3 3
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#endif /* __DW_UDC_H */
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