mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
e985eb14ac
This converts the following to Kconfig: CONFIG_CMD_ASKENV CONFIG_CMD_BMP CONFIG_CMD_BOOTD CONFIG_CMD_CACHE CONFIG_CMD_CRC32 CONFIG_CMD_DHCP CONFIG_CMD_ENV CONFIG_CMD_EXPORTENV CONFIG_CMD_EXT2 CONFIG_CMD_EXT4 CONFIG_CMD_FLASH CONFIG_CMD_FS_GENERIC CONFIG_CMD_FUSE CONFIG_CMD_GPIO CONFIG_CMD_GPT CONFIG_CMD_GREPENV CONFIG_CMD_I2C CONFIG_CMD_IMLS CONFIG_CMD_IMPORTENV CONFIG_CMD_LOADB CONFIG_CMD_LOADS CONFIG_CMD_MEMINFO CONFIG_CMD_MII CONFIG_CMD_MTDPARTS CONFIG_CMD_NAND CONFIG_CMD_NAND_TRIMFFS CONFIG_CMD_NFS CONFIG_CMD_PCA953X CONFIG_CMD_PCA953X_INFO CONFIG_CMD_PCI CONFIG_CMD_PING CONFIG_CMD_READ CONFIG_CMD_SF CONFIG_CMD_SPI CONFIG_CMD_SPL CONFIG_CMD_SPL_WRITE_SIZE CONFIG_CMD_TIME CONFIG_CMD_TRACE CONFIG_CMD_UBI CONFIG_CMD_UBIFS CONFIG_CMD_UNZIP CONFIG_FS_EXT4 Signed-off-by: Tom Rini <trini@konsulko.com>
72 lines
1.8 KiB
C
72 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de>
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*/
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#ifndef _CONFIG_DB_88F6720_H
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#define _CONFIG_DB_88F6720_H
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/*
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* High Level Configuration Options (easy to change)
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*/
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/*
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* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
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* for DDR ECC byte filling in the SPL before loading the main
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* U-Boot into it.
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*/
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#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MVTWSI
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#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
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#define CONFIG_SYS_I2C_SLAVE 0x0
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#define CONFIG_SYS_I2C_SPEED 100000
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/* USB/EHCI configuration */
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#define CONFIG_EHCI_IS_TDI
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
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/* Environment in SPI NOR flash */
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#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
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/*
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* mv-common.h should be defined after CMD configs since it used them
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* to enable certain macros
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*/
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#include "mv-common.h"
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/*
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* Memory layout while starting into the bin_hdr via the
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* BootROM:
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*
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* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
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* 0x4000.4030 bin_hdr start address
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* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
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* 0x4007.fffc BootROM stack top
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*
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* The address space between 0x4007.fffc and 0x400f.fff is not locked in
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* L2 cache thus cannot be used.
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*/
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/* SPL */
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/* Defines for SPL */
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#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
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#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
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#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MALLOC_SIMPLE
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#endif
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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/* SPL related SPI defines */
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#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
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#endif /* _CONFIG_DB_88F6720_H */
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