mirror of
https://github.com/brain-hackers/u-boot-brain
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35b65dd8ef
Historically, the reset_cpu() function had an `addr` parameter which was
meant to pass in an address of the reset vector location, where the CPU
should reset to. This feature is no longer used anywhere in U-Boot as
all reset_cpu() implementations now ignore the passed value. Generic
code has been added which always calls reset_cpu() with `0` which means
this feature can no longer be used easily anyway.
Over time, many implementations seem to have "misunderstood" the
existence of this parameter as a way to customize/parameterize the reset
(e.g. COLD vs WARM resets). As this is not properly supported, the
code will almost always not do what it is intended to (because all
call-sites just call reset_cpu() with 0).
To avoid confusion and to clean up the codebase from unused left-overs
of the past, remove the `addr` parameter entirely. Code which intends
to support different kinds of resets should be rewritten as a sysreset
driver instead.
This transformation was done with the following coccinelle patch:
@@
expression argvalue;
@@
- reset_cpu(argvalue)
+ reset_cpu()
@@
identifier argname;
type argtype;
@@
- reset_cpu(argtype argname)
+ reset_cpu(void)
{ ... }
Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
97 lines
2.1 KiB
C
97 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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/*
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* MX7ULP WDOG Register Map
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*/
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struct wdog_regs {
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u8 cs1;
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u8 cs2;
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u16 reserve0;
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u32 cnt;
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u32 toval;
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u32 win;
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};
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#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
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#define CONFIG_WATCHDOG_TIMEOUT_MSECS 0x1500
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#endif
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#define REFRESH_WORD0 0xA602 /* 1st refresh word */
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#define REFRESH_WORD1 0xB480 /* 2nd refresh word */
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#define UNLOCK_WORD0 0xC520 /* 1st unlock word */
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#define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
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#define WDGCS1_WDGE (1<<7)
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#define WDGCS1_WDGUPDATE (1<<5)
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#define WDGCS2_FLG (1<<6)
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#define WDG_BUS_CLK (0x0)
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#define WDG_LPO_CLK (0x1)
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#define WDG_32KHZ_CLK (0x2)
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#define WDG_EXT_CLK (0x3)
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void hw_watchdog_set_timeout(u16 val)
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{
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/* setting timeout value */
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
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writel(val, &wdog->toval);
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}
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void hw_watchdog_reset(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
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writel(REFRESH_WORD0, &wdog->cnt);
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writel(REFRESH_WORD1, &wdog->cnt);
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}
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void hw_watchdog_init(void)
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{
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u8 val;
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
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writel(UNLOCK_WORD0, &wdog->cnt);
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writel(UNLOCK_WORD1, &wdog->cnt);
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val = readb(&wdog->cs2);
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val |= WDGCS2_FLG;
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writeb(val, &wdog->cs2);
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hw_watchdog_set_timeout(CONFIG_WATCHDOG_TIMEOUT_MSECS);
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writel(0, &wdog->win);
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writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */
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writeb((WDGCS1_WDGE | WDGCS1_WDGUPDATE), &wdog->cs1);/* enable counter running */
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hw_watchdog_reset();
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}
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void reset_cpu(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
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writel(UNLOCK_WORD0, &wdog->cnt);
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writel(UNLOCK_WORD1, &wdog->cnt);
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hw_watchdog_set_timeout(5); /* 5ms timeout */
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writel(0, &wdog->win);
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writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */
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writeb(WDGCS1_WDGE, &wdog->cs1);/* enable counter running */
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hw_watchdog_reset();
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while (1);
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}
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