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https://github.com/brain-hackers/u-boot-brain
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41575d8e4c
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
426 lines
9.8 KiB
C
426 lines
9.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* max98088.c -- MAX98088 ALSA SoC Audio driver
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*
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* Copyright 2010 Maxim Integrated Products
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*
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* Modified for U-Boot by Chih-Chung Chang (chihchung@chromium.org),
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* following the changes made in max98095.c
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*/
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#include <common.h>
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#include <audio_codec.h>
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#include <div64.h>
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#include <dm.h>
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#include <i2c.h>
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#include <i2s.h>
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#include <log.h>
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#include <sound.h>
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#include <asm/gpio.h>
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#include "maxim_codec.h"
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#include "max98088.h"
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/* codec mclk clock divider coefficients. Index 0 is reserved. */
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static const int rate_table[] = {0, 8000, 11025, 16000, 22050, 24000, 32000,
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44100, 48000, 88200, 96000};
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/*
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* codec mclk clock divider coefficients based on sampling rate
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*
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* @param rate sampling rate
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* @param value address of indexvalue to be stored
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*
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* @return 0 for success or negative error code.
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*/
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static int rate_value(int rate, u8 *value)
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{
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int i;
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for (i = 1; i < ARRAY_SIZE(rate_table); i++) {
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if (rate_table[i] >= rate) {
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*value = i;
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return 0;
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}
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}
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*value = 1;
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return -EINVAL;
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}
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/*
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* Sets hw params for max98088
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*
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* @priv: max98088 information pointer
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* @rate: Sampling rate
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* @bits_per_sample: Bits per sample
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*
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* @return -EIO for error, 0 for success.
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*/
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int max98088_hw_params(struct maxim_priv *priv, unsigned int rate,
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unsigned int bits_per_sample)
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{
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int error;
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u8 regval;
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switch (bits_per_sample) {
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case 16:
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error = maxim_bic_or(priv, M98088_REG_DAI1_FORMAT,
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M98088_DAI_WS, 0);
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break;
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case 24:
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error = maxim_bic_or(priv, M98088_REG_DAI1_FORMAT,
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M98088_DAI_WS, M98088_DAI_WS);
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break;
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default:
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debug("%s: Illegal bits per sample %d.\n",
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__func__, bits_per_sample);
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return -EINVAL;
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}
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error |= maxim_bic_or(priv, M98088_REG_PWR_SYS, M98088_SHDNRUN, 0);
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if (rate_value(rate, ®val)) {
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debug("%s: Failed to set sample rate to %d.\n",
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__func__, rate);
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return -EIO;
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}
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error |= maxim_bic_or(priv, M98088_REG_DAI1_CLKMODE,
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M98088_CLKMODE_MASK, regval << 4);
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priv->rate = rate;
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/* Update sample rate mode */
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if (rate < 50000)
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error |= maxim_bic_or(priv, M98088_REG_DAI1_FILTERS,
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M98088_DAI_DHF, 0);
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else
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error |= maxim_bic_or(priv, M98088_REG_DAI1_FILTERS,
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M98088_DAI_DHF, M98088_DAI_DHF);
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error |= maxim_bic_or(priv, M98088_REG_PWR_SYS, M98088_SHDNRUN,
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M98088_SHDNRUN);
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if (error < 0) {
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debug("%s: Error setting hardware params.\n", __func__);
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return -EIO;
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}
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priv->rate = rate;
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return 0;
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}
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/*
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* Configures Audio interface system clock for the given frequency
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*
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* @priv: max98088 information
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* @freq: Sampling frequency in Hz
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*
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* @return -EIO for error, 0 for success.
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*/
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int max98088_set_sysclk(struct maxim_priv *priv, unsigned int freq)
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{
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int error = 0;
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u8 pwr;
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/* Requested clock frequency is already setup */
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if (freq == priv->sysclk)
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return 0;
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/*
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* Setup clocks for slave mode, and using the PLL
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* PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
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* 0x02 (when master clk is 20MHz to 30MHz)..
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*/
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if (freq >= 10000000 && freq < 20000000) {
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error = maxim_i2c_write(priv, M98088_REG_SYS_CLK, 0x10);
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} else if ((freq >= 20000000) && (freq < 30000000)) {
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error = maxim_i2c_write(priv, M98088_REG_SYS_CLK, 0x20);
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} else {
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debug("%s: Invalid master clock frequency\n", __func__);
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return -EIO;
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}
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error |= maxim_i2c_read(priv, M98088_REG_PWR_SYS, &pwr);
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if (pwr & M98088_SHDNRUN) {
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error |= maxim_bic_or(priv, M98088_REG_PWR_SYS,
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M98088_SHDNRUN, 0);
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error |= maxim_bic_or(priv, M98088_REG_PWR_SYS,
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M98088_SHDNRUN, M98088_SHDNRUN);
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}
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debug("%s: Clock at %uHz\n", __func__, freq);
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if (error < 0)
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return -EIO;
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priv->sysclk = freq;
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return 0;
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}
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/*
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* Sets Max98090 I2S format
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*
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* @priv: max98088 information
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* @fmt: i2S format - supports a subset of the options defined in i2s.h.
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*
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* @return -EIO for error, 0 for success.
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*/
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int max98088_set_fmt(struct maxim_priv *priv, int fmt)
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{
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u8 reg15val;
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u8 reg14val = 0;
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int error = 0;
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if (fmt == priv->fmt)
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return 0;
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priv->fmt = fmt;
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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/* Slave mode PLL */
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error |= maxim_i2c_write(priv, M98088_REG_DAI1_CLKCFG_HI,
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0x80);
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error |= maxim_i2c_write(priv, M98088_REG_DAI1_CLKCFG_LO,
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0x00);
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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/* Set to master mode */
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reg14val |= M98088_DAI_MAS;
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break;
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case SND_SOC_DAIFMT_CBS_CFM:
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case SND_SOC_DAIFMT_CBM_CFS:
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default:
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debug("%s: Clock mode unsupported\n", __func__);
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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reg14val |= M98088_DAI_DLY;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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break;
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default:
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debug("%s: Unrecognized format.\n", __func__);
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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break;
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case SND_SOC_DAIFMT_NB_IF:
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reg14val |= M98088_DAI_WCI;
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break;
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case SND_SOC_DAIFMT_IB_NF:
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reg14val |= M98088_DAI_BCI;
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break;
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case SND_SOC_DAIFMT_IB_IF:
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reg14val |= M98088_DAI_BCI | M98088_DAI_WCI;
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break;
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default:
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debug("%s: Unrecognized inversion settings.\n", __func__);
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return -EINVAL;
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}
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error |= maxim_bic_or(priv, M98088_REG_DAI1_FORMAT,
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M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
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M98088_DAI_WCI, reg14val);
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reg15val = M98088_DAI_BSEL64;
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error |= maxim_i2c_write(priv, M98088_REG_DAI1_CLOCK, reg15val);
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if (error < 0) {
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debug("%s: Error setting i2s format.\n", __func__);
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return -EIO;
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}
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return 0;
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}
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/*
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* max98088_reset() - reset the audio codec
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*
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* @priv: max98088 information
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* @return -EIO for error, 0 for success.
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*/
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static int max98088_reset(struct maxim_priv *priv)
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{
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int ret, i;
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u8 val;
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/*
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* Reset to hardware default for registers, as there is not a soft
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* reset hardware control register.
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*/
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for (i = M98088_REG_IRQ_ENABLE; i <= M98088_REG_PWR_SYS; i++) {
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switch (i) {
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case M98088_REG_BIAS_CNTL:
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val = 0xf0;
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break;
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case M98088_REG_DAC_BIAS2:
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val = 0x0f;
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break;
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default:
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val = 0;
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}
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ret = maxim_i2c_write(priv, i, val);
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if (ret < 0) {
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debug("%s: Failed to reset: %d\n", __func__, ret);
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return ret;
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}
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}
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return 0;
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}
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/**
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* max98088_device_init() - Initialise max98088 codec device
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*
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* @priv: max98088 information
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*
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* @return -EIO for error, 0 for success.
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*/
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static int max98088_device_init(struct maxim_priv *priv)
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{
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unsigned char id;
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int error = 0;
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/* reset the codec, the DSP core, and disable all interrupts */
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error = max98088_reset(priv);
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if (error != 0) {
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debug("Reset\n");
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return error;
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}
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/* initialize private data */
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priv->sysclk = -1U;
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priv->rate = -1U;
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priv->fmt = -1U;
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error = maxim_i2c_read(priv, M98088_REG_REV_ID, &id);
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if (error < 0) {
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debug("%s: Failure reading hardware revision: %d\n",
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__func__, id);
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return -EIO;
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}
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debug("%s: Hardware revision: %d\n", __func__, id);
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return 0;
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}
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static int max98088_setup_interface(struct maxim_priv *priv)
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{
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int error;
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/* Reading interrupt status to clear them */
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error = maxim_i2c_write(priv, M98088_REG_PWR_SYS, M98088_PWRSV);
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error |= maxim_i2c_write(priv, M98088_REG_IRQ_ENABLE, 0x00);
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/*
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* initialize registers to hardware default configuring audio
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* interface2 to DAI1
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*/
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error |= maxim_i2c_write(priv, M98088_REG_MIX_DAC,
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M98088_DAI1L_TO_DACL | M98088_DAI1R_TO_DACR);
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error |= maxim_i2c_write(priv, M98088_REG_BIAS_CNTL, 0xF0);
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error |= maxim_i2c_write(priv, M98088_REG_DAC_BIAS2, 0x0F);
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error |= maxim_i2c_write(priv, M98088_REG_DAI1_IOCFG,
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M98088_S2NORMAL | M98088_SDATA);
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/*
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* route DACL and DACR output to headphone and speakers
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* Ordering: DACL, DACR, DACL, DACR
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*/
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error |= maxim_i2c_write(priv, M98088_REG_MIX_SPK_LEFT, 1);
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error |= maxim_i2c_write(priv, M98088_REG_MIX_SPK_RIGHT, 1);
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error |= maxim_i2c_write(priv, M98088_REG_MIX_HP_LEFT, 1);
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error |= maxim_i2c_write(priv, M98088_REG_MIX_HP_RIGHT, 1);
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/* set volume: -12db */
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error |= maxim_i2c_write(priv, M98088_REG_LVL_SPK_L, 0x0f);
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error |= maxim_i2c_write(priv, M98088_REG_LVL_SPK_R, 0x0f);
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/* set volume: -22db */
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error |= maxim_i2c_write(priv, M98088_REG_LVL_HP_L, 0x0d);
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error |= maxim_i2c_write(priv, M98088_REG_LVL_HP_R, 0x0d);
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/* power enable */
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error |= maxim_i2c_write(priv, M98088_REG_PWR_EN_OUT,
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M98088_HPLEN | M98088_HPREN | M98088_SPLEN |
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M98088_SPREN | M98088_DALEN | M98088_DAREN);
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if (error < 0)
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return -EIO;
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return 0;
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}
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static int max98088_do_init(struct maxim_priv *priv, int sampling_rate,
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int mclk_freq, int bits_per_sample)
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{
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int ret = 0;
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ret = max98088_setup_interface(priv);
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if (ret < 0) {
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debug("%s: max98088 setup interface failed\n", __func__);
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return ret;
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}
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ret = max98088_set_sysclk(priv, mclk_freq);
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if (ret < 0) {
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debug("%s: max98088 codec set sys clock failed\n", __func__);
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return ret;
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}
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ret = max98088_hw_params(priv, sampling_rate, bits_per_sample);
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if (ret == 0) {
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ret = max98088_set_fmt(priv, SND_SOC_DAIFMT_I2S |
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SND_SOC_DAIFMT_NB_NF |
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SND_SOC_DAIFMT_CBS_CFS);
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}
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return ret;
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}
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static int max98088_set_params(struct udevice *dev, int interface, int rate,
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int mclk_freq, int bits_per_sample,
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uint channels)
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{
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struct maxim_priv *priv = dev_get_priv(dev);
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return max98088_do_init(priv, rate, mclk_freq, bits_per_sample);
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}
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static int max98088_probe(struct udevice *dev)
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{
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struct maxim_priv *priv = dev_get_priv(dev);
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int ret;
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priv->dev = dev;
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ret = max98088_device_init(priv);
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if (ret < 0) {
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debug("%s: max98088 codec chip init failed\n", __func__);
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return ret;
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}
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return 0;
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}
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static const struct audio_codec_ops max98088_ops = {
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.set_params = max98088_set_params,
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};
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static const struct udevice_id max98088_ids[] = {
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{ .compatible = "maxim,max98088" },
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{ }
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};
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U_BOOT_DRIVER(max98088) = {
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.name = "max98088",
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.id = UCLASS_AUDIO_CODEC,
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.of_match = max98088_ids,
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.probe = max98088_probe,
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.ops = &max98088_ops,
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.priv_auto = sizeof(struct maxim_priv),
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};
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