mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 15:26:03 +09:00
b0db69b4e1
Something was wrong in the merge process into the mainline. Some added patches access driver structure fields and functions that have been modified by previous patches. The patch renames: - dev_get_platdata to dev_get_plat - dev_get_uclass_platdata to dev_get_uclass_plat - ofdata_to_platdata to of_to_plat - plat_data_alloc_size to plat_auto - priv_auto_alloc_size to priv_auto - video_uc_platdata to video_uc_plat Signed-off-by: Dario Binacchi <dariobin@libero.it>
469 lines
12 KiB
C
469 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* EHRPWM PWM driver
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*
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* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
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*
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* Based on Linux kernel drivers/pwm/pwm-tiehrpwm.c
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*/
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#include <common.h>
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#include <clk.h>
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#include <div64.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <pwm.h>
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#include <asm/io.h>
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#define NSEC_PER_SEC 1000000000L
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/* Time base module registers */
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#define TI_EHRPWM_TBCTL 0x00
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#define TI_EHRPWM_TBPRD 0x0A
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#define TI_EHRPWM_TBCTL_PRDLD_MASK BIT(3)
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#define TI_EHRPWM_TBCTL_PRDLD_SHDW 0
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#define TI_EHRPWM_TBCTL_PRDLD_IMDT BIT(3)
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#define TI_EHRPWM_TBCTL_CLKDIV_MASK GENMASK(12, 7)
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#define TI_EHRPWM_TBCTL_CTRMODE_MASK GENMASK(1, 0)
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#define TI_EHRPWM_TBCTL_CTRMODE_UP 0
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#define TI_EHRPWM_TBCTL_CTRMODE_DOWN BIT(0)
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#define TI_EHRPWM_TBCTL_CTRMODE_UPDOWN BIT(1)
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#define TI_EHRPWM_TBCTL_CTRMODE_FREEZE GENMASK(1, 0)
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#define TI_EHRPWM_TBCTL_HSPCLKDIV_SHIFT 7
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#define TI_EHRPWM_TBCTL_CLKDIV_SHIFT 10
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#define TI_EHRPWM_CLKDIV_MAX 7
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#define TI_EHRPWM_HSPCLKDIV_MAX 7
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#define TI_EHRPWM_PERIOD_MAX 0xFFFF
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/* Counter compare module registers */
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#define TI_EHRPWM_CMPA 0x12
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#define TI_EHRPWM_CMPB 0x14
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/* Action qualifier module registers */
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#define TI_EHRPWM_AQCTLA 0x16
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#define TI_EHRPWM_AQCTLB 0x18
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#define TI_EHRPWM_AQSFRC 0x1A
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#define TI_EHRPWM_AQCSFRC 0x1C
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#define TI_EHRPWM_AQCTL_CBU_MASK GENMASK(9, 8)
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#define TI_EHRPWM_AQCTL_CBU_FRCLOW BIT(8)
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#define TI_EHRPWM_AQCTL_CBU_FRCHIGH BIT(9)
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#define TI_EHRPWM_AQCTL_CBU_FRCTOGGLE GENMASK(9, 8)
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#define TI_EHRPWM_AQCTL_CAU_MASK GENMASK(5, 4)
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#define TI_EHRPWM_AQCTL_CAU_FRCLOW BIT(4)
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#define TI_EHRPWM_AQCTL_CAU_FRCHIGH BIT(5)
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#define TI_EHRPWM_AQCTL_CAU_FRCTOGGLE GENMASK(5, 4)
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#define TI_EHRPWM_AQCTL_PRD_MASK GENMASK(3, 2)
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#define TI_EHRPWM_AQCTL_PRD_FRCLOW BIT(2)
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#define TI_EHRPWM_AQCTL_PRD_FRCHIGH BIT(3)
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#define TI_EHRPWM_AQCTL_PRD_FRCTOGGLE GENMASK(3, 2)
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#define TI_EHRPWM_AQCTL_ZRO_MASK GENMASK(1, 0)
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#define TI_EHRPWM_AQCTL_ZRO_FRCLOW BIT(0)
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#define TI_EHRPWM_AQCTL_ZRO_FRCHIGH BIT(1)
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#define TI_EHRPWM_AQCTL_ZRO_FRCTOGGLE GENMASK(1, 0)
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#define TI_EHRPWM_AQCTL_CHANA_POLNORMAL (TI_EHRPWM_AQCTL_CAU_FRCLOW | \
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TI_EHRPWM_AQCTL_PRD_FRCHIGH | \
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TI_EHRPWM_AQCTL_ZRO_FRCHIGH)
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#define TI_EHRPWM_AQCTL_CHANA_POLINVERSED (TI_EHRPWM_AQCTL_CAU_FRCHIGH | \
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TI_EHRPWM_AQCTL_PRD_FRCLOW | \
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TI_EHRPWM_AQCTL_ZRO_FRCLOW)
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#define TI_EHRPWM_AQCTL_CHANB_POLNORMAL (TI_EHRPWM_AQCTL_CBU_FRCLOW | \
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TI_EHRPWM_AQCTL_PRD_FRCHIGH | \
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TI_EHRPWM_AQCTL_ZRO_FRCHIGH)
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#define TI_EHRPWM_AQCTL_CHANB_POLINVERSED (TI_EHRPWM_AQCTL_CBU_FRCHIGH | \
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TI_EHRPWM_AQCTL_PRD_FRCLOW | \
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TI_EHRPWM_AQCTL_ZRO_FRCLOW)
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#define TI_EHRPWM_AQSFRC_RLDCSF_MASK GENMASK(7, 6)
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#define TI_EHRPWM_AQSFRC_RLDCSF_ZRO 0
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#define TI_EHRPWM_AQSFRC_RLDCSF_PRD BIT(6)
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#define TI_EHRPWM_AQSFRC_RLDCSF_ZROPRD BIT(7)
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#define TI_EHRPWM_AQSFRC_RLDCSF_IMDT GENMASK(7, 6)
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#define TI_EHRPWM_AQCSFRC_CSFB_MASK GENMASK(3, 2)
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#define TI_EHRPWM_AQCSFRC_CSFB_FRCDIS 0
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#define TI_EHRPWM_AQCSFRC_CSFB_FRCLOW BIT(2)
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#define TI_EHRPWM_AQCSFRC_CSFB_FRCHIGH BIT(3)
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#define TI_EHRPWM_AQCSFRC_CSFB_DISSWFRC GENMASK(3, 2)
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#define TI_EHRPWM_AQCSFRC_CSFA_MASK GENMASK(1, 0)
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#define TI_EHRPWM_AQCSFRC_CSFA_FRCDIS 0
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#define TI_EHRPWM_AQCSFRC_CSFA_FRCLOW BIT(0)
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#define TI_EHRPWM_AQCSFRC_CSFA_FRCHIGH BIT(1)
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#define TI_EHRPWM_AQCSFRC_CSFA_DISSWFRC GENMASK(1, 0)
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#define TI_EHRPWM_NUM_CHANNELS 2
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struct ti_ehrpwm_priv {
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fdt_addr_t regs;
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u32 clk_rate;
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struct clk tbclk;
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unsigned long period_cycles[TI_EHRPWM_NUM_CHANNELS];
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bool polarity_reversed[TI_EHRPWM_NUM_CHANNELS];
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};
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static void ti_ehrpwm_modify(u16 val, u16 mask, fdt_addr_t reg)
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{
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unsigned short v;
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v = readw(reg);
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v &= ~mask;
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v |= val & mask;
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writew(v, reg);
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}
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static int ti_ehrpwm_set_invert(struct udevice *dev, uint channel,
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bool polarity)
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{
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struct ti_ehrpwm_priv *priv = dev_get_priv(dev);
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if (channel >= TI_EHRPWM_NUM_CHANNELS)
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return -ENOSPC;
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/* Configuration of polarity in hardware delayed, do at enable */
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priv->polarity_reversed[channel] = polarity;
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return 0;
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}
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/**
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* set_prescale_div - Set up the prescaler divider function
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* @rqst_prescaler: prescaler value min
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* @prescale_div: prescaler value set
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* @tb_clk_div: Time Base Control prescaler bits
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*/
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static int set_prescale_div(unsigned long rqst_prescaler, u16 *prescale_div,
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u16 *tb_clk_div)
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{
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unsigned int clkdiv, hspclkdiv;
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for (clkdiv = 0; clkdiv <= TI_EHRPWM_CLKDIV_MAX; clkdiv++) {
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for (hspclkdiv = 0; hspclkdiv <= TI_EHRPWM_HSPCLKDIV_MAX;
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hspclkdiv++) {
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/*
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* calculations for prescaler value :
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* prescale_div = HSPCLKDIVIDER * CLKDIVIDER.
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* HSPCLKDIVIDER = 2 ** hspclkdiv
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* CLKDIVIDER = (1), if clkdiv == 0 *OR*
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* (2 * clkdiv), if clkdiv != 0
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*
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* Configure prescale_div value such that period
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* register value is less than 65535.
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*/
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*prescale_div = (1 << clkdiv) *
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(hspclkdiv ? (hspclkdiv * 2) : 1);
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if (*prescale_div > rqst_prescaler) {
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*tb_clk_div =
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(clkdiv << TI_EHRPWM_TBCTL_CLKDIV_SHIFT) |
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(hspclkdiv <<
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TI_EHRPWM_TBCTL_HSPCLKDIV_SHIFT);
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return 0;
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}
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}
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}
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return 1;
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}
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static void ti_ehrpwm_configure_polarity(struct udevice *dev, uint channel)
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{
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struct ti_ehrpwm_priv *priv = dev_get_priv(dev);
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u16 aqctl_val, aqctl_mask;
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unsigned int aqctl_reg;
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/*
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* Configure PWM output to HIGH/LOW level on counter
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* reaches compare register value and LOW/HIGH level
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* on counter value reaches period register value and
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* zero value on counter
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*/
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if (channel == 1) {
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aqctl_reg = TI_EHRPWM_AQCTLB;
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aqctl_mask = TI_EHRPWM_AQCTL_CBU_MASK;
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if (priv->polarity_reversed[channel])
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aqctl_val = TI_EHRPWM_AQCTL_CHANB_POLINVERSED;
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else
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aqctl_val = TI_EHRPWM_AQCTL_CHANB_POLNORMAL;
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} else {
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aqctl_reg = TI_EHRPWM_AQCTLA;
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aqctl_mask = TI_EHRPWM_AQCTL_CAU_MASK;
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if (priv->polarity_reversed[channel])
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aqctl_val = TI_EHRPWM_AQCTL_CHANA_POLINVERSED;
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else
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aqctl_val = TI_EHRPWM_AQCTL_CHANA_POLNORMAL;
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}
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aqctl_mask |= TI_EHRPWM_AQCTL_PRD_MASK | TI_EHRPWM_AQCTL_ZRO_MASK;
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ti_ehrpwm_modify(aqctl_val, aqctl_mask, priv->regs + aqctl_reg);
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}
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/*
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* period_ns = 10^9 * (ps_divval * period_cycles) / PWM_CLK_RATE
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* duty_ns = 10^9 * (ps_divval * duty_cycles) / PWM_CLK_RATE
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*/
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static int ti_ehrpwm_set_config(struct udevice *dev, uint channel,
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uint period_ns, uint duty_ns)
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{
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struct ti_ehrpwm_priv *priv = dev_get_priv(dev);
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u32 period_cycles, duty_cycles;
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u16 ps_divval, tb_divval;
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unsigned int i, cmp_reg;
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unsigned long long c;
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if (channel >= TI_EHRPWM_NUM_CHANNELS)
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return -ENOSPC;
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if (period_ns > NSEC_PER_SEC)
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return -ERANGE;
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c = priv->clk_rate;
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c = c * period_ns;
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do_div(c, NSEC_PER_SEC);
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period_cycles = (unsigned long)c;
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if (period_cycles < 1) {
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period_cycles = 1;
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duty_cycles = 1;
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} else {
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c = priv->clk_rate;
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c = c * duty_ns;
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do_div(c, NSEC_PER_SEC);
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duty_cycles = (unsigned long)c;
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}
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dev_dbg(dev, "channel=%d, period_ns=%d, duty_ns=%d\n",
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channel, period_ns, duty_ns);
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/*
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* Period values should be same for multiple PWM channels as IP uses
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* same period register for multiple channels.
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*/
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for (i = 0; i < TI_EHRPWM_NUM_CHANNELS; i++) {
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if (priv->period_cycles[i] &&
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priv->period_cycles[i] != period_cycles) {
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/*
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* Allow channel to reconfigure period if no other
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* channels being configured.
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*/
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if (i == channel)
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continue;
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dev_err(dev, "period value conflicts with channel %u\n",
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i);
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return -EINVAL;
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}
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}
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priv->period_cycles[channel] = period_cycles;
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/* Configure clock prescaler to support Low frequency PWM wave */
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if (set_prescale_div(period_cycles / TI_EHRPWM_PERIOD_MAX, &ps_divval,
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&tb_divval)) {
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dev_err(dev, "unsupported values\n");
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return -EINVAL;
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}
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/* Update clock prescaler values */
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ti_ehrpwm_modify(tb_divval, TI_EHRPWM_TBCTL_CLKDIV_MASK,
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priv->regs + TI_EHRPWM_TBCTL);
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/* Update period & duty cycle with presacler division */
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period_cycles = period_cycles / ps_divval;
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duty_cycles = duty_cycles / ps_divval;
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/* Configure shadow loading on Period register */
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ti_ehrpwm_modify(TI_EHRPWM_TBCTL_PRDLD_SHDW, TI_EHRPWM_TBCTL_PRDLD_MASK,
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priv->regs + TI_EHRPWM_TBCTL);
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writew(period_cycles, priv->regs + TI_EHRPWM_TBPRD);
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/* Configure ehrpwm counter for up-count mode */
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ti_ehrpwm_modify(TI_EHRPWM_TBCTL_CTRMODE_UP,
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TI_EHRPWM_TBCTL_CTRMODE_MASK,
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priv->regs + TI_EHRPWM_TBCTL);
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if (channel == 1)
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/* Channel 1 configured with compare B register */
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cmp_reg = TI_EHRPWM_CMPB;
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else
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/* Channel 0 configured with compare A register */
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cmp_reg = TI_EHRPWM_CMPA;
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writew(duty_cycles, priv->regs + cmp_reg);
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return 0;
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}
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static int ti_ehrpwm_disable(struct udevice *dev, uint channel)
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{
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struct ti_ehrpwm_priv *priv = dev_get_priv(dev);
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u16 aqcsfrc_val, aqcsfrc_mask;
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int err;
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if (channel >= TI_EHRPWM_NUM_CHANNELS)
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return -ENOSPC;
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/* Action Qualifier puts PWM output low forcefully */
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if (channel) {
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aqcsfrc_val = TI_EHRPWM_AQCSFRC_CSFB_FRCLOW;
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aqcsfrc_mask = TI_EHRPWM_AQCSFRC_CSFB_MASK;
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} else {
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aqcsfrc_val = TI_EHRPWM_AQCSFRC_CSFA_FRCLOW;
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aqcsfrc_mask = TI_EHRPWM_AQCSFRC_CSFA_MASK;
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}
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/* Update shadow register first before modifying active register */
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ti_ehrpwm_modify(TI_EHRPWM_AQSFRC_RLDCSF_ZRO,
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TI_EHRPWM_AQSFRC_RLDCSF_MASK,
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priv->regs + TI_EHRPWM_AQSFRC);
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ti_ehrpwm_modify(aqcsfrc_val, aqcsfrc_mask,
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priv->regs + TI_EHRPWM_AQCSFRC);
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/*
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* Changes to immediate action on Action Qualifier. This puts
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* Action Qualifier control on PWM output from next TBCLK
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*/
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ti_ehrpwm_modify(TI_EHRPWM_AQSFRC_RLDCSF_IMDT,
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TI_EHRPWM_AQSFRC_RLDCSF_MASK,
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priv->regs + TI_EHRPWM_AQSFRC);
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ti_ehrpwm_modify(aqcsfrc_val, aqcsfrc_mask,
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priv->regs + TI_EHRPWM_AQCSFRC);
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/* Disabling TBCLK on PWM disable */
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err = clk_disable(&priv->tbclk);
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if (err) {
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dev_err(dev, "failed to disable tbclk\n");
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return err;
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}
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return 0;
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}
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static int ti_ehrpwm_enable(struct udevice *dev, uint channel)
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{
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struct ti_ehrpwm_priv *priv = dev_get_priv(dev);
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u16 aqcsfrc_val, aqcsfrc_mask;
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int err;
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if (channel >= TI_EHRPWM_NUM_CHANNELS)
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return -ENOSPC;
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/* Disabling Action Qualifier on PWM output */
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if (channel) {
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aqcsfrc_val = TI_EHRPWM_AQCSFRC_CSFB_FRCDIS;
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aqcsfrc_mask = TI_EHRPWM_AQCSFRC_CSFB_MASK;
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} else {
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aqcsfrc_val = TI_EHRPWM_AQCSFRC_CSFA_FRCDIS;
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aqcsfrc_mask = TI_EHRPWM_AQCSFRC_CSFA_MASK;
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}
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/* Changes to shadow mode */
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ti_ehrpwm_modify(TI_EHRPWM_AQSFRC_RLDCSF_ZRO,
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TI_EHRPWM_AQSFRC_RLDCSF_MASK,
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priv->regs + TI_EHRPWM_AQSFRC);
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ti_ehrpwm_modify(aqcsfrc_val, aqcsfrc_mask,
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priv->regs + TI_EHRPWM_AQCSFRC);
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/* Channels polarity can be configured from action qualifier module */
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ti_ehrpwm_configure_polarity(dev, channel);
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err = clk_enable(&priv->tbclk);
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if (err) {
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dev_err(dev, "failed to enable tbclk\n");
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return err;
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}
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return 0;
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}
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static int ti_ehrpwm_set_enable(struct udevice *dev, uint channel, bool enable)
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{
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if (enable)
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return ti_ehrpwm_enable(dev, channel);
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return ti_ehrpwm_disable(dev, channel);
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}
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static int ti_ehrpwm_of_to_plat(struct udevice *dev)
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{
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struct ti_ehrpwm_priv *priv = dev_get_priv(dev);
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priv->regs = dev_read_addr(dev);
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if (priv->regs == FDT_ADDR_T_NONE) {
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dev_err(dev, "invalid address\n");
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return -EINVAL;
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}
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dev_dbg(dev, "regs=0x%08lx\n", priv->regs);
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return 0;
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}
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static int ti_ehrpwm_remove(struct udevice *dev)
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{
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struct ti_ehrpwm_priv *priv = dev_get_priv(dev);
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clk_release_all(&priv->tbclk, 1);
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return 0;
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}
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static int ti_ehrpwm_probe(struct udevice *dev)
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{
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struct ti_ehrpwm_priv *priv = dev_get_priv(dev);
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struct clk clk;
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int err;
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err = clk_get_by_name(dev, "fck", &clk);
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if (err) {
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dev_err(dev, "failed to get clock\n");
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return err;
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}
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priv->clk_rate = clk_get_rate(&clk);
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if (IS_ERR_VALUE(priv->clk_rate) || !priv->clk_rate) {
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dev_err(dev, "failed to get clock rate\n");
|
|
if (IS_ERR_VALUE(priv->clk_rate))
|
|
return priv->clk_rate;
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Acquire tbclk for Time Base EHRPWM submodule */
|
|
err = clk_get_by_name(dev, "tbclk", &priv->tbclk);
|
|
if (err) {
|
|
dev_err(dev, "failed to get tbclk clock\n");
|
|
return err;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct pwm_ops ti_ehrpwm_ops = {
|
|
.set_config = ti_ehrpwm_set_config,
|
|
.set_enable = ti_ehrpwm_set_enable,
|
|
.set_invert = ti_ehrpwm_set_invert,
|
|
};
|
|
|
|
static const struct udevice_id ti_ehrpwm_ids[] = {
|
|
{.compatible = "ti,am3352-ehrpwm"},
|
|
{.compatible = "ti,am33xx-ehrpwm"},
|
|
{}
|
|
};
|
|
|
|
U_BOOT_DRIVER(ti_ehrpwm) = {
|
|
.name = "ti_ehrpwm",
|
|
.id = UCLASS_PWM,
|
|
.of_match = ti_ehrpwm_ids,
|
|
.ops = &ti_ehrpwm_ops,
|
|
.of_to_plat = ti_ehrpwm_of_to_plat,
|
|
.probe = ti_ehrpwm_probe,
|
|
.remove = ti_ehrpwm_remove,
|
|
.priv_auto = sizeof(struct ti_ehrpwm_priv),
|
|
};
|