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https://github.com/brain-hackers/u-boot-brain
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41575d8e4c
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
256 lines
6.8 KiB
C
256 lines
6.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Meson GXL and GXM USB2 PHY driver
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*
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* Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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* Copyright (C) 2018 BayLibre, SAS
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* Author: Neil Armstrong <narmstron@baylibre.com>
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*/
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#include <common.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <bitfield.h>
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#include <dm.h>
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#include <errno.h>
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#include <generic-phy.h>
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#include <regmap.h>
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#include <linux/delay.h>
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#include <power/regulator.h>
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#include <clk.h>
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#include <linux/usb/otg.h>
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#include <asm/arch/usb-gx.h>
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#include <linux/bitops.h>
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#include <linux/compat.h>
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/* bits [31:27] are read-only */
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#define U2P_R0 0x0
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#define U2P_R0_BYPASS_SEL BIT(0)
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#define U2P_R0_BYPASS_DM_EN BIT(1)
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#define U2P_R0_BYPASS_DP_EN BIT(2)
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#define U2P_R0_TXBITSTUFF_ENH BIT(3)
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#define U2P_R0_TXBITSTUFF_EN BIT(4)
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#define U2P_R0_DM_PULLDOWN BIT(5)
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#define U2P_R0_DP_PULLDOWN BIT(6)
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#define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7)
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#define U2P_R0_DP_VBUS_VLD_EXT BIT(8)
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#define U2P_R0_ADP_PRB_EN BIT(9)
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#define U2P_R0_ADP_DISCHARGE BIT(10)
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#define U2P_R0_ADP_CHARGE BIT(11)
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#define U2P_R0_DRV_VBUS BIT(12)
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#define U2P_R0_ID_PULLUP BIT(13)
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#define U2P_R0_LOOPBACK_EN_B BIT(14)
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#define U2P_R0_OTG_DISABLE BIT(15)
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#define U2P_R0_COMMON_ONN BIT(16)
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#define U2P_R0_FSEL_MASK GENMASK(19, 17)
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#define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20)
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#define U2P_R0_POWER_ON_RESET BIT(22)
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#define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23)
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#define U2P_R0_ID_SET_ID_DQ BIT(25)
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#define U2P_R0_ATE_RESET BIT(26)
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#define U2P_R0_FSV_MINUS BIT(27)
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#define U2P_R0_FSV_PLUS BIT(28)
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#define U2P_R0_BYPASS_DM_DATA BIT(29)
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#define U2P_R0_BYPASS_DP_DATA BIT(30)
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#define U2P_R1 0x4
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#define U2P_R1_BURN_IN_TEST BIT(0)
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#define U2P_R1_ACA_ENABLE BIT(1)
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#define U2P_R1_DCD_ENABLE BIT(2)
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#define U2P_R1_VDAT_SRC_EN_B BIT(3)
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#define U2P_R1_VDAT_DET_EN_B BIT(4)
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#define U2P_R1_CHARGES_SEL BIT(5)
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#define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6)
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#define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7)
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#define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9)
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#define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11)
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#define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13)
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#define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17)
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#define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21)
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#define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23)
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#define U2P_R1_SQRX_TUNE_MASK GENMASK(28, 26)
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#define U2P_R1_COMP_DIS_TUNE_MASK GENMASK(31, 29)
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/* bits [31:14] are read-only */
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#define U2P_R2 0x8
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#define U2P_R2_TESTDATA_IN_MASK GENMASK(7, 0)
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#define U2P_R2_TESTADDR_MASK GENMASK(11, 8)
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#define U2P_R2_TESTDATA_OUT_SEL BIT(12)
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#define U2P_R2_TESTCLK BIT(13)
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#define U2P_R2_TESTDATA_OUT_MASK GENMASK(17, 14)
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#define U2P_R2_ACA_PIN_RANGE_C BIT(18)
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#define U2P_R2_ACA_PIN_RANGE_B BIT(19)
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#define U2P_R2_ACA_PIN_RANGE_A BIT(20)
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#define U2P_R2_ACA_PIN_GND BIT(21)
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#define U2P_R2_ACA_PIN_FLOAT BIT(22)
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#define U2P_R2_CHARGE_DETECT BIT(23)
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#define U2P_R2_DEVICE_SESSION_VALID BIT(24)
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#define U2P_R2_ADP_PROBE BIT(25)
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#define U2P_R2_ADP_SENSE BIT(26)
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#define U2P_R2_SESSION_END BIT(27)
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#define U2P_R2_VBUS_VALID BIT(28)
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#define U2P_R2_B_VALID BIT(29)
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#define U2P_R2_A_VALID BIT(30)
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#define U2P_R2_ID_DIG BIT(31)
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#define U2P_R3 0xc
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#define RESET_COMPLETE_TIME 500
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struct phy_meson_gxl_usb2_priv {
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struct regmap *regmap;
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#if CONFIG_IS_ENABLED(DM_REGULATOR)
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struct udevice *phy_supply;
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#endif
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#if CONFIG_IS_ENABLED(CLK)
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struct clk clk;
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#endif
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};
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static void phy_meson_gxl_usb2_reset(struct phy_meson_gxl_usb2_priv *priv)
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{
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uint val;
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regmap_read(priv->regmap, U2P_R0, &val);
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/* reset the PHY and wait until settings are stabilized */
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val |= U2P_R0_POWER_ON_RESET;
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regmap_write(priv->regmap, U2P_R0, val);
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udelay(RESET_COMPLETE_TIME);
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val &= ~U2P_R0_POWER_ON_RESET;
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regmap_write(priv->regmap, U2P_R0, val);
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udelay(RESET_COMPLETE_TIME);
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}
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void phy_meson_gxl_usb2_set_mode(struct phy *phy, enum usb_dr_mode mode)
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{
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struct udevice *dev = phy->dev;
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struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
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uint val;
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regmap_read(priv->regmap, U2P_R0, &val);
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switch (mode) {
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case USB_DR_MODE_UNKNOWN:
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case USB_DR_MODE_HOST:
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case USB_DR_MODE_OTG:
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val |= U2P_R0_DM_PULLDOWN;
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val |= U2P_R0_DP_PULLDOWN;
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val &= ~U2P_R0_ID_PULLUP;
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break;
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case USB_DR_MODE_PERIPHERAL:
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val &= ~U2P_R0_DM_PULLDOWN;
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val &= ~U2P_R0_DP_PULLDOWN;
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val |= U2P_R0_ID_PULLUP;
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break;
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}
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regmap_write(priv->regmap, U2P_R0, val);
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phy_meson_gxl_usb2_reset(priv);
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}
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static int phy_meson_gxl_usb2_power_on(struct phy *phy)
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{
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struct udevice *dev = phy->dev;
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struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
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uint val;
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regmap_read(priv->regmap, U2P_R0, &val);
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/* power on the PHY by taking it out of reset mode */
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val &= ~U2P_R0_POWER_ON_RESET;
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regmap_write(priv->regmap, U2P_R0, val);
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phy_meson_gxl_usb2_set_mode(phy, USB_DR_MODE_HOST);
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#if CONFIG_IS_ENABLED(DM_REGULATOR)
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if (priv->phy_supply) {
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int ret = regulator_set_enable(priv->phy_supply, true);
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if (ret)
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return ret;
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}
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#endif
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return 0;
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}
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static int phy_meson_gxl_usb2_power_off(struct phy *phy)
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{
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struct udevice *dev = phy->dev;
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struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
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uint val;
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regmap_read(priv->regmap, U2P_R0, &val);
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/* power off the PHY by putting it into reset mode */
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val |= U2P_R0_POWER_ON_RESET;
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regmap_write(priv->regmap, U2P_R0, val);
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#if CONFIG_IS_ENABLED(DM_REGULATOR)
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if (priv->phy_supply) {
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int ret = regulator_set_enable(priv->phy_supply, false);
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if (ret) {
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pr_err("Error disabling PHY supply\n");
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return ret;
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}
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}
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#endif
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return 0;
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}
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struct phy_ops meson_gxl_usb2_phy_ops = {
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.power_on = phy_meson_gxl_usb2_power_on,
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.power_off = phy_meson_gxl_usb2_power_off,
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};
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int meson_gxl_usb2_phy_probe(struct udevice *dev)
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{
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struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
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int ret;
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ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
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if (ret)
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return ret;
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#if CONFIG_IS_ENABLED(CLK)
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ret = clk_get_by_index(dev, 0, &priv->clk);
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if (ret < 0)
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return ret;
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ret = clk_enable(&priv->clk);
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if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
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pr_err("failed to enable PHY clock\n");
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clk_free(&priv->clk);
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return ret;
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}
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#endif
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#if CONFIG_IS_ENABLED(DM_REGULATOR)
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ret = device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
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if (ret && ret != -ENOENT) {
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pr_err("Failed to get PHY regulator\n");
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return ret;
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}
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#endif
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return 0;
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}
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static const struct udevice_id meson_gxl_usb2_phy_ids[] = {
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{ .compatible = "amlogic,meson-gxl-usb2-phy" },
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{ }
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};
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U_BOOT_DRIVER(meson_gxl_usb2_phy) = {
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.name = "meson_gxl_usb2_phy",
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.id = UCLASS_PHY,
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.of_match = meson_gxl_usb2_phy_ids,
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.probe = meson_gxl_usb2_phy_probe,
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.ops = &meson_gxl_usb2_phy_ops,
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.priv_auto = sizeof(struct phy_meson_gxl_usb2_priv),
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};
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