mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 15:26:03 +09:00
d26b739afe
dm9000 has code to detect and initialize external phy parts, but later on in the code the part is forced to use the internal phy unconditionally. Remove the unused/untested code. change the GPIO initialization so that only the GPIO used as an internal phy reset (hardwired in the chip) is set as an output. The remaining GPIO need to be handled by board specific code to prevent possible drive conflicts. Set as inputs for safety. replace a few magic numbers with defines Signed-off-by: Andrew Dyer <adyer@righthandtech.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
141 lines
3.5 KiB
C
141 lines
3.5 KiB
C
/*
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* dm9000 Ethernet
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*/
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#ifdef CONFIG_DRIVER_DM9000
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#define DM9000_ID 0x90000A46
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#define DM9000_PKT_MAX 1536 /* Received packet max size */
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#define DM9000_PKT_RDY 0x01 /* Packet ready to receive */
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/* although the registers are 16 bit, they are 32-bit aligned.
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*/
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#define DM9000_NCR 0x00
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#define DM9000_NSR 0x01
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#define DM9000_TCR 0x02
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#define DM9000_TSR1 0x03
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#define DM9000_TSR2 0x04
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#define DM9000_RCR 0x05
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#define DM9000_RSR 0x06
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#define DM9000_ROCR 0x07
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#define DM9000_BPTR 0x08
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#define DM9000_FCTR 0x09
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#define DM9000_FCR 0x0A
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#define DM9000_EPCR 0x0B
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#define DM9000_EPAR 0x0C
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#define DM9000_EPDRL 0x0D
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#define DM9000_EPDRH 0x0E
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#define DM9000_WCR 0x0F
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#define DM9000_PAR 0x10
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#define DM9000_MAR 0x16
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#define DM9000_GPCR 0x1e
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#define DM9000_GPR 0x1f
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#define DM9000_TRPAL 0x22
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#define DM9000_TRPAH 0x23
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#define DM9000_RWPAL 0x24
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#define DM9000_RWPAH 0x25
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#define DM9000_VIDL 0x28
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#define DM9000_VIDH 0x29
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#define DM9000_PIDL 0x2A
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#define DM9000_PIDH 0x2B
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#define DM9000_CHIPR 0x2C
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#define DM9000_SMCR 0x2F
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#define DM9000_PHY 0x40 /* PHY address 0x01 */
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#define DM9000_MRCMDX 0xF0
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#define DM9000_MRCMD 0xF2
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#define DM9000_MRRL 0xF4
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#define DM9000_MRRH 0xF5
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#define DM9000_MWCMDX 0xF6
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#define DM9000_MWCMD 0xF8
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#define DM9000_MWRL 0xFA
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#define DM9000_MWRH 0xFB
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#define DM9000_TXPLL 0xFC
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#define DM9000_TXPLH 0xFD
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#define DM9000_ISR 0xFE
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#define DM9000_IMR 0xFF
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#define NCR_EXT_PHY (1<<7)
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#define NCR_WAKEEN (1<<6)
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#define NCR_FCOL (1<<4)
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#define NCR_FDX (1<<3)
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#define NCR_LBK (3<<1)
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#define NCR_LBK_INT_MAC (1<<1)
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#define NCR_LBK_INT_PHY (2<<1)
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#define NCR_RST (1<<0)
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#define NSR_SPEED (1<<7)
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#define NSR_LINKST (1<<6)
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#define NSR_WAKEST (1<<5)
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#define NSR_TX2END (1<<3)
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#define NSR_TX1END (1<<2)
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#define NSR_RXOV (1<<1)
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#define TCR_TJDIS (1<<6)
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#define TCR_EXCECM (1<<5)
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#define TCR_PAD_DIS2 (1<<4)
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#define TCR_CRC_DIS2 (1<<3)
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#define TCR_PAD_DIS1 (1<<2)
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#define TCR_CRC_DIS1 (1<<1)
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#define TCR_TXREQ (1<<0)
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#define TSR_TJTO (1<<7)
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#define TSR_LC (1<<6)
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#define TSR_NC (1<<5)
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#define TSR_LCOL (1<<4)
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#define TSR_COL (1<<3)
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#define TSR_EC (1<<2)
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#define RCR_WTDIS (1<<6)
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#define RCR_DIS_LONG (1<<5)
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#define RCR_DIS_CRC (1<<4)
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#define RCR_ALL (1<<3)
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#define RCR_RUNT (1<<2)
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#define RCR_PRMSC (1<<1)
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#define RCR_RXEN (1<<0)
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#define RSR_RF (1<<7)
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#define RSR_MF (1<<6)
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#define RSR_LCS (1<<5)
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#define RSR_RWTO (1<<4)
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#define RSR_PLE (1<<3)
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#define RSR_AE (1<<2)
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#define RSR_CE (1<<1)
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#define RSR_FOE (1<<0)
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#define EPCR_EPOS_PHY (1<<3)
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#define EPCR_EPOS_EE (0<<3)
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#define EPCR_ERPRR (1<<2)
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#define EPCR_ERPRW (1<<1)
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#define EPCR_ERRE (1<<0)
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#define FCTR_HWOT(ot) (( ot & 0xf ) << 4 )
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#define FCTR_LWOT(ot) ( ot & 0xf )
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#define BPTR_BPHW(x) ((x) << 4)
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#define BPTR_JPT_200US (0x07)
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#define BPTR_JPT_600US (0x0f)
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#define IMR_PAR (1<<7)
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#define IMR_ROOM (1<<3)
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#define IMR_ROM (1<<2)
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#define IMR_PTM (1<<1)
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#define IMR_PRM (1<<0)
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#define ISR_ROOS (1<<3)
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#define ISR_ROS (1<<2)
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#define ISR_PTS (1<<1)
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#define ISR_PRS (1<<0)
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#define GPCR_GPIO0_OUT (1<<0)
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#define GPR_PHY_PWROFF (1<<0)
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#endif
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