mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
249 lines
11 KiB
C
249 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef CS8900_H
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#define CS8900_H
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/*
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* Cirrus Logic CS8900A Ethernet
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*
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* (C) 2009 Ben Warren , biggerbadderben@gmail.com
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* Converted to use CONFIG_NET_MULTI API
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* Copyright (C) 1999 Ben Williamson <benw@pobox.com>
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*
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* This program is loaded into SRAM in bootstrap mode, where it waits
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* for commands on UART1 to read and write memory, jump to code etc.
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* A design goal for this program is to be entirely independent of the
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* target board. Anything with a CL-PS7111 or EP7211 should be able to run
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* this code in bootstrap mode. All the board specifics can be handled on
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* the host.
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*/
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#include <asm/types.h>
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#include <config.h>
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#define CS8900_DRIVERNAME "CS8900"
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/* although the registers are 16 bit, they are 32-bit aligned on the
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EDB7111. so we have to read them as 32-bit registers and ignore the
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upper 16-bits. i'm not sure if this holds for the EDB7211. */
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#ifdef CONFIG_CS8900_BUS16
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/* 16 bit aligned registers, 16 bit wide */
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#define CS8900_REG u16
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#elif defined(CONFIG_CS8900_BUS32)
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/* 32 bit aligned registers, 16 bit wide (we ignore upper 16 bits) */
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#define CS8900_REG u32
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#else
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#error unknown bussize ...
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#endif
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struct cs8900_regs {
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CS8900_REG rtdata;
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CS8900_REG pad0;
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CS8900_REG txcmd;
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CS8900_REG txlen;
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CS8900_REG isq;
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CS8900_REG pptr;
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CS8900_REG pdata;
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};
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struct cs8900_priv {
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struct cs8900_regs *regs;
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};
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#define ISQ_RxEvent 0x04
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#define ISQ_TxEvent 0x08
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#define ISQ_BufEvent 0x0C
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#define ISQ_RxMissEvent 0x10
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#define ISQ_TxColEvent 0x12
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#define ISQ_EventMask 0x3F
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/* packet page register offsets */
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/* bus interface registers */
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#define PP_ChipID 0x0000 /* Chip identifier - must be 0x630E */
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#define PP_ChipRev 0x0002 /* Chip revision, model codes */
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#define PP_IntReg 0x0022 /* Interrupt configuration */
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#define PP_IntReg_IRQ0 0x0000 /* Use INTR0 pin */
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#define PP_IntReg_IRQ1 0x0001 /* Use INTR1 pin */
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#define PP_IntReg_IRQ2 0x0002 /* Use INTR2 pin */
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#define PP_IntReg_IRQ3 0x0003 /* Use INTR3 pin */
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/* status and control registers */
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#define PP_RxCFG 0x0102 /* Receiver configuration */
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#define PP_RxCFG_Skip1 0x0040 /* Skip (i.e. discard) current frame */
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#define PP_RxCFG_Stream 0x0080 /* Enable streaming mode */
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#define PP_RxCFG_RxOK 0x0100 /* RxOK interrupt enable */
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#define PP_RxCFG_RxDMAonly 0x0200 /* Use RxDMA for all frames */
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#define PP_RxCFG_AutoRxDMA 0x0400 /* Select RxDMA automatically */
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#define PP_RxCFG_BufferCRC 0x0800 /* Include CRC characters in frame */
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#define PP_RxCFG_CRC 0x1000 /* Enable interrupt on CRC error */
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#define PP_RxCFG_RUNT 0x2000 /* Enable interrupt on RUNT frames */
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#define PP_RxCFG_EXTRA 0x4000 /* Enable interrupt on frames with extra data */
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#define PP_RxCTL 0x0104 /* Receiver control */
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#define PP_RxCTL_IAHash 0x0040 /* Accept frames that match hash */
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#define PP_RxCTL_Promiscuous 0x0080 /* Accept any frame */
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#define PP_RxCTL_RxOK 0x0100 /* Accept well formed frames */
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#define PP_RxCTL_Multicast 0x0200 /* Accept multicast frames */
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#define PP_RxCTL_IA 0x0400 /* Accept frame that matches IA */
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#define PP_RxCTL_Broadcast 0x0800 /* Accept broadcast frames */
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#define PP_RxCTL_CRC 0x1000 /* Accept frames with bad CRC */
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#define PP_RxCTL_RUNT 0x2000 /* Accept runt frames */
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#define PP_RxCTL_EXTRA 0x4000 /* Accept frames that are too long */
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#define PP_TxCFG 0x0106 /* Transmit configuration */
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#define PP_TxCFG_CRS 0x0040 /* Enable interrupt on loss of carrier */
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#define PP_TxCFG_SQE 0x0080 /* Enable interrupt on Signal Quality Error */
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#define PP_TxCFG_TxOK 0x0100 /* Enable interrupt on successful xmits */
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#define PP_TxCFG_Late 0x0200 /* Enable interrupt on "out of window" */
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#define PP_TxCFG_Jabber 0x0400 /* Enable interrupt on jabber detect */
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#define PP_TxCFG_Collision 0x0800 /* Enable interrupt if collision */
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#define PP_TxCFG_16Collisions 0x8000 /* Enable interrupt if > 16 collisions */
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#define PP_TxCmd 0x0108 /* Transmit command status */
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#define PP_TxCmd_TxStart_5 0x0000 /* Start after 5 bytes in buffer */
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#define PP_TxCmd_TxStart_381 0x0040 /* Start after 381 bytes in buffer */
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#define PP_TxCmd_TxStart_1021 0x0080 /* Start after 1021 bytes in buffer */
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#define PP_TxCmd_TxStart_Full 0x00C0 /* Start after all bytes loaded */
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#define PP_TxCmd_Force 0x0100 /* Discard any pending packets */
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#define PP_TxCmd_OneCollision 0x0200 /* Abort after a single collision */
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#define PP_TxCmd_NoCRC 0x1000 /* Do not add CRC */
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#define PP_TxCmd_NoPad 0x2000 /* Do not pad short packets */
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#define PP_BufCFG 0x010A /* Buffer configuration */
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#define PP_BufCFG_SWI 0x0040 /* Force interrupt via software */
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#define PP_BufCFG_RxDMA 0x0080 /* Enable interrupt on Rx DMA */
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#define PP_BufCFG_TxRDY 0x0100 /* Enable interrupt when ready for Tx */
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#define PP_BufCFG_TxUE 0x0200 /* Enable interrupt in Tx underrun */
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#define PP_BufCFG_RxMiss 0x0400 /* Enable interrupt on missed Rx packets */
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#define PP_BufCFG_Rx128 0x0800 /* Enable Rx interrupt after 128 bytes */
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#define PP_BufCFG_TxCol 0x1000 /* Enable int on Tx collision ctr overflow */
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#define PP_BufCFG_Miss 0x2000 /* Enable int on Rx miss ctr overflow */
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#define PP_BufCFG_RxDest 0x8000 /* Enable int on Rx dest addr match */
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#define PP_LineCTL 0x0112 /* Line control */
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#define PP_LineCTL_Rx 0x0040 /* Enable receiver */
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#define PP_LineCTL_Tx 0x0080 /* Enable transmitter */
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#define PP_LineCTL_AUIonly 0x0100 /* AUI interface only */
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#define PP_LineCTL_AutoAUI10BT 0x0200 /* Autodetect AUI or 10BaseT interface */
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#define PP_LineCTL_ModBackoffE 0x0800 /* Enable modified backoff algorithm */
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#define PP_LineCTL_PolarityDis 0x1000 /* Disable Rx polarity autodetect */
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#define PP_LineCTL_2partDefDis 0x2000 /* Disable two-part defferal */
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#define PP_LineCTL_LoRxSquelch 0x4000 /* Reduce receiver squelch threshold */
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#define PP_SelfCTL 0x0114 /* Chip self control */
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#define PP_SelfCTL_Reset 0x0040 /* Self-clearing reset */
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#define PP_SelfCTL_SWSuspend 0x0100 /* Initiate suspend mode */
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#define PP_SelfCTL_HWSleepE 0x0200 /* Enable SLEEP input */
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#define PP_SelfCTL_HWStandbyE 0x0400 /* Enable standby mode */
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#define PP_SelfCTL_HC0E 0x1000 /* use HCB0 for LINK LED */
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#define PP_SelfCTL_HC1E 0x2000 /* use HCB1 for BSTATUS LED */
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#define PP_SelfCTL_HCB0 0x4000 /* control LINK LED if HC0E set */
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#define PP_SelfCTL_HCB1 0x8000 /* control BSTATUS LED if HC1E set */
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#define PP_BusCTL 0x0116 /* Bus control */
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#define PP_BusCTL_ResetRxDMA 0x0040 /* Reset RxDMA pointer */
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#define PP_BusCTL_DMAextend 0x0100 /* Extend DMA cycle */
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#define PP_BusCTL_UseSA 0x0200 /* Assert MEMCS16 on address decode */
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#define PP_BusCTL_MemoryE 0x0400 /* Enable memory mode */
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#define PP_BusCTL_DMAburst 0x0800 /* Limit DMA access burst */
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#define PP_BusCTL_IOCHRDYE 0x1000 /* Set IOCHRDY high impedence */
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#define PP_BusCTL_RxDMAsize 0x2000 /* Set DMA buffer size 64KB */
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#define PP_BusCTL_EnableIRQ 0x8000 /* Generate interrupt on interrupt event */
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#define PP_TestCTL 0x0118 /* Test control */
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#define PP_TestCTL_DisableLT 0x0080 /* Disable link status */
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#define PP_TestCTL_ENDECloop 0x0200 /* Internal loopback */
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#define PP_TestCTL_AUIloop 0x0400 /* AUI loopback */
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#define PP_TestCTL_DisBackoff 0x0800 /* Disable backoff algorithm */
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#define PP_TestCTL_FDX 0x4000 /* Enable full duplex mode */
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#define PP_ISQ 0x0120 /* Interrupt Status Queue */
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#define PP_RER 0x0124 /* Receive event */
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#define PP_RER_IAHash 0x0040 /* Frame hash match */
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#define PP_RER_Dribble 0x0080 /* Frame had 1-7 extra bits after last byte */
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#define PP_RER_RxOK 0x0100 /* Frame received with no errors */
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#define PP_RER_Hashed 0x0200 /* Frame address hashed OK */
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#define PP_RER_IA 0x0400 /* Frame address matched IA */
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#define PP_RER_Broadcast 0x0800 /* Broadcast frame */
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#define PP_RER_CRC 0x1000 /* Frame had CRC error */
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#define PP_RER_RUNT 0x2000 /* Runt frame */
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#define PP_RER_EXTRA 0x4000 /* Frame was too long */
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#define PP_TER 0x0128 /* Transmit event */
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#define PP_TER_CRS 0x0040 /* Carrier lost */
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#define PP_TER_SQE 0x0080 /* Signal Quality Error */
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#define PP_TER_TxOK 0x0100 /* Packet sent without error */
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#define PP_TER_Late 0x0200 /* Out of window */
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#define PP_TER_Jabber 0x0400 /* Stuck transmit? */
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#define PP_TER_NumCollisions 0x7800 /* Number of collisions */
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#define PP_TER_16Collisions 0x8000 /* > 16 collisions */
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#define PP_BER 0x012C /* Buffer event */
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#define PP_BER_SWint 0x0040 /* Software interrupt */
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#define PP_BER_RxDMAFrame 0x0080 /* Received framed DMAed */
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#define PP_BER_Rdy4Tx 0x0100 /* Ready for transmission */
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#define PP_BER_TxUnderrun 0x0200 /* Transmit underrun */
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#define PP_BER_RxMiss 0x0400 /* Received frame missed */
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#define PP_BER_Rx128 0x0800 /* 128 bytes received */
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#define PP_BER_RxDest 0x8000 /* Received framed passed address filter */
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#define PP_RxMiss 0x0130 /* Receiver miss counter */
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#define PP_TxCol 0x0132 /* Transmit collision counter */
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#define PP_LineSTAT 0x0134 /* Line status */
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#define PP_LineSTAT_LinkOK 0x0080 /* Line is connected and working */
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#define PP_LineSTAT_AUI 0x0100 /* Connected via AUI */
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#define PP_LineSTAT_10BT 0x0200 /* Connected via twisted pair */
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#define PP_LineSTAT_Polarity 0x1000 /* Line polarity OK (10BT only) */
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#define PP_LineSTAT_CRS 0x4000 /* Frame being received */
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#define PP_SelfSTAT 0x0136 /* Chip self status */
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#define PP_SelfSTAT_33VActive 0x0040 /* supply voltage is 3.3V */
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#define PP_SelfSTAT_InitD 0x0080 /* Chip initialization complete */
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#define PP_SelfSTAT_SIBSY 0x0100 /* EEPROM is busy */
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#define PP_SelfSTAT_EEPROM 0x0200 /* EEPROM present */
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#define PP_SelfSTAT_EEPROM_OK 0x0400 /* EEPROM checks out */
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#define PP_SelfSTAT_ELPresent 0x0800 /* External address latch logic available */
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#define PP_SelfSTAT_EEsize 0x1000 /* Size of EEPROM */
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#define PP_BusSTAT 0x0138 /* Bus status */
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#define PP_BusSTAT_TxBid 0x0080 /* Tx error */
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#define PP_BusSTAT_TxRDY 0x0100 /* Ready for Tx data */
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#define PP_TDR 0x013C /* AUI Time Domain Reflectometer */
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/* initiate transmit registers */
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#define PP_TxCommand 0x0144 /* Tx Command */
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#define PP_TxLength 0x0146 /* Tx Length */
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/* address filter registers */
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#define PP_LAF 0x0150 /* Logical address filter (6 bytes) */
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#define PP_IA 0x0158 /* Individual address (MAC) */
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/* EEPROM Kram */
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#define SI_BUSY 0x0100
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#define PP_EECMD 0x0040 /* NVR Interface Command register */
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#define PP_EEData 0x0042 /* NVR Interface Data Register */
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#define EEPROM_WRITE_EN 0x00F0
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#define EEPROM_WRITE_DIS 0x0000
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#define EEPROM_WRITE_CMD 0x0100
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#define EEPROM_READ_CMD 0x0200
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#define EEPROM_ERASE_CMD 0x0300
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/* Exported functions */
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int cs8900_e2prom_read(struct eth_device *dev, uchar, ushort *);
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int cs8900_e2prom_write(struct eth_device *dev, uchar, ushort);
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#endif /* CS8900_H */
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