mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 15:26:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
224 lines
6.6 KiB
C
224 lines
6.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2014 Broadcom Corporation.
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*/
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#ifndef _BCM_SF2_ETH_GMAC_H_
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#define _BCM_SF2_ETH_GMAC_H_
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#define BCM_SF2_ETH_MAC_NAME "gmac"
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#ifndef ETHHW_PORT_INT
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#define ETHHW_PORT_INT 8
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#endif
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#define GMAC0_REG_BASE 0x18042000
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#define GMAC0_DEV_CTRL_ADDR GMAC0_REG_BASE
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#define GMAC0_INT_STATUS_ADDR (GMAC0_REG_BASE + 0x020)
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#define GMAC0_INTR_RECV_LAZY_ADDR (GMAC0_REG_BASE + 0x100)
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#define GMAC0_PHY_CTRL_ADDR (GMAC0_REG_BASE + 0x188)
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#define GMAC_DMA_PTR_OFFSET 0x04
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#define GMAC_DMA_ADDR_LOW_OFFSET 0x08
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#define GMAC_DMA_ADDR_HIGH_OFFSET 0x0c
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#define GMAC_DMA_STATUS0_OFFSET 0x10
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#define GMAC_DMA_STATUS1_OFFSET 0x14
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#define GMAC0_DMA_TX_CTRL_ADDR (GMAC0_REG_BASE + 0x200)
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#define GMAC0_DMA_TX_PTR_ADDR \
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(GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET)
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#define GMAC0_DMA_TX_ADDR_LOW_ADDR \
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(GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET)
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#define GMAC0_DMA_TX_ADDR_HIGH_ADDR \
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(GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET)
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#define GMAC0_DMA_TX_STATUS0_ADDR \
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(GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET)
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#define GMAC0_DMA_TX_STATUS1_ADDR \
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(GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET)
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#define GMAC0_DMA_RX_CTRL_ADDR (GMAC0_REG_BASE + 0x220)
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#define GMAC0_DMA_RX_PTR_ADDR \
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(GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET)
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#define GMAC0_DMA_RX_ADDR_LOW_ADDR \
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(GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET)
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#define GMAC0_DMA_RX_ADDR_HIGH_ADDR \
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(GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET)
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#define GMAC0_DMA_RX_STATUS0_ADDR \
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(GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET)
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#define GMAC0_DMA_RX_STATUS1_ADDR \
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(GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET)
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#define UNIMAC0_CMD_CFG_ADDR (GMAC0_REG_BASE + 0x808)
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#define UNIMAC0_MAC_MSB_ADDR (GMAC0_REG_BASE + 0x80c)
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#define UNIMAC0_MAC_LSB_ADDR (GMAC0_REG_BASE + 0x810)
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#define UNIMAC0_FRM_LENGTH_ADDR (GMAC0_REG_BASE + 0x814)
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#define GMAC0_IRL_FRAMECOUNT_SHIFT 24
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/* transmit channel control */
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/* transmit enable */
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#define D64_XC_XE 0x00000001
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/* transmit suspend request */
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#define D64_XC_SE 0x00000002
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/* parity check disable */
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#define D64_XC_PD 0x00000800
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/* BurstLen bits */
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#define D64_XC_BL_MASK 0x001C0000
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#define D64_XC_BL_SHIFT 18
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/* transmit descriptor table pointer */
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/* last valid descriptor */
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#define D64_XP_LD_MASK 0x00001fff
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/* transmit channel status */
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/* transmit state */
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#define D64_XS0_XS_MASK 0xf0000000
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#define D64_XS0_XS_SHIFT 28
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#define D64_XS0_XS_DISABLED 0x00000000
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#define D64_XS0_XS_ACTIVE 0x10000000
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#define D64_XS0_XS_IDLE 0x20000000
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#define D64_XS0_XS_STOPPED 0x30000000
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#define D64_XS0_XS_SUSP 0x40000000
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/* receive channel control */
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/* receive enable */
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#define D64_RC_RE 0x00000001
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/* address extension bits */
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#define D64_RC_AE 0x00030000
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/* overflow continue */
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#define D64_RC_OC 0x00000400
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/* parity check disable */
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#define D64_RC_PD 0x00000800
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/* receive frame offset */
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#define D64_RC_RO_MASK 0x000000fe
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#define D64_RC_RO_SHIFT 1
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/* BurstLen bits */
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#define D64_RC_BL_MASK 0x001C0000
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#define D64_RC_BL_SHIFT 18
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/* flags for dma controller */
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/* partity enable */
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#define DMA_CTRL_PEN (1 << 0)
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/* rx overflow continue */
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#define DMA_CTRL_ROC (1 << 1)
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/* receive descriptor table pointer */
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/* last valid descriptor */
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#define D64_RP_LD_MASK 0x00001fff
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/* receive channel status */
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/* current descriptor pointer */
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#define D64_RS0_CD_MASK 0x00001fff
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/* receive state */
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#define D64_RS0_RS_MASK 0xf0000000
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#define D64_RS0_RS_SHIFT 28
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#define D64_RS0_RS_DISABLED 0x00000000
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#define D64_RS0_RS_ACTIVE 0x10000000
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#define D64_RS0_RS_IDLE 0x20000000
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#define D64_RS0_RS_STOPPED 0x30000000
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#define D64_RS0_RS_SUSP 0x40000000
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/* descriptor control flags 1 */
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/* core specific flags */
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#define D64_CTRL_COREFLAGS 0x0ff00000
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/* end of descriptor table */
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#define D64_CTRL1_EOT ((uint32_t)1 << 28)
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/* interrupt on completion */
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#define D64_CTRL1_IOC ((uint32_t)1 << 29)
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/* end of frame */
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#define D64_CTRL1_EOF ((uint32_t)1 << 30)
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/* start of frame */
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#define D64_CTRL1_SOF ((uint32_t)1 << 31)
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/* descriptor control flags 2 */
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/* buffer byte count. real data len must <= 16KB */
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#define D64_CTRL2_BC_MASK 0x00007fff
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/* address extension bits */
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#define D64_CTRL2_AE 0x00030000
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#define D64_CTRL2_AE_SHIFT 16
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/* parity bit */
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#define D64_CTRL2_PARITY 0x00040000
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/* control flags in the range [27:20] are core-specific and not defined here */
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#define D64_CTRL_CORE_MASK 0x0ff00000
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#define DC_MROR 0x00000010
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#define PC_MTE 0x00800000
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/* command config */
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#define CC_TE 0x00000001
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#define CC_RE 0x00000002
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#define CC_ES_MASK 0x0000000c
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#define CC_ES_SHIFT 2
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#define CC_PROM 0x00000010
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#define CC_PAD_EN 0x00000020
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#define CC_CF 0x00000040
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#define CC_PF 0x00000080
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#define CC_RPI 0x00000100
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#define CC_TAI 0x00000200
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#define CC_HD 0x00000400
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#define CC_HD_SHIFT 10
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#define CC_SR 0x00002000
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#define CC_ML 0x00008000
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#define CC_AE 0x00400000
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#define CC_CFE 0x00800000
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#define CC_NLC 0x01000000
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#define CC_RL 0x02000000
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#define CC_RED 0x04000000
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#define CC_PE 0x08000000
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#define CC_TPI 0x10000000
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#define CC_AT 0x20000000
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#define I_PDEE 0x00000400
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#define I_PDE 0x00000800
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#define I_DE 0x00001000
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#define I_RDU 0x00002000
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#define I_RFO 0x00004000
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#define I_XFU 0x00008000
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#define I_RI 0x00010000
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#define I_XI0 0x01000000
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#define I_XI1 0x02000000
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#define I_XI2 0x04000000
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#define I_XI3 0x08000000
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#define I_ERRORS (I_PDEE | I_PDE | I_DE | I_RDU | I_RFO | I_XFU)
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#define DEF_INTMASK (I_XI0 | I_XI1 | I_XI2 | I_XI3 | I_RI | I_ERRORS)
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#define I_INTMASK 0x0f01fcff
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#define CHIP_DRU_BASE 0x0301d000
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#define CRMU_CHIP_IO_PAD_CONTROL_ADDR (CHIP_DRU_BASE + 0x0bc)
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#define SWITCH_GLOBAL_CONFIG_ADDR (CHIP_DRU_BASE + 0x194)
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#define CDRU_IOMUX_FORCE_PAD_IN_SHIFT 0
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#define CDRU_SWITCH_BYPASS_SWITCH_SHIFT 13
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#define AMAC0_IDM_RESET_ADDR 0x18110800
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#define AMAC0_IO_CTRL_DIRECT_ADDR 0x18110408
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#define AMAC0_IO_CTRL_CLK_250_SEL_SHIFT 6
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#define AMAC0_IO_CTRL_GMII_MODE_SHIFT 5
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#define AMAC0_IO_CTRL_DEST_SYNC_MODE_EN_SHIFT 3
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#define CHIPA_CHIP_ID_ADDR 0x18000000
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#define CHIPID (readl(CHIPA_CHIP_ID_ADDR) & 0xFFFF)
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#define CHIPREV (((readl(CHIPA_CHIP_ID_ADDR) >> 16) & 0xF)
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#define CHIPSKU (((readl(CHIPA_CHIP_ID_ADDR) >> 20) & 0xF)
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#define GMAC_MII_CTRL_ADDR 0x18002000
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#define GMAC_MII_CTRL_BYP_SHIFT 10
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#define GMAC_MII_CTRL_EXT_SHIFT 9
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#define GMAC_MII_DATA_ADDR 0x18002004
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#define GMAC_MII_DATA_READ_CMD 0x60020000
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#define GMAC_MII_DATA_WRITE_CMD 0x50020000
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#define GMAC_MII_BUSY_SHIFT 8
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#define GMAC_MII_PHY_ADDR_SHIFT 23
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#define GMAC_MII_PHY_REG_SHIFT 18
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#define GMAC_RESET_DELAY 2
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#define HWRXOFF 30
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#define MAXNAMEL 8
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#define NUMTXQ 4
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int gmac_add(struct eth_device *dev);
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#endif /* _BCM_SF2_ETH_GMAC_H_ */
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