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https://github.com/brain-hackers/u-boot-brain
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372286217f
Allow L1 Icache & L1 Dcache line size to be specified separately, since there's no architectural mandate that they be the same. The [id]cache_line_size functions are tidied up to take advantage of the fact that the Kconfig entries are always present to simply check them for zero rather than needing to #ifdef on their presence. Signed-off-by: Paul Burton <paul.burton@imgtec.com> [removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
31 lines
390 B
Plaintext
31 lines
390 B
Plaintext
if BOARD_TPLINK_WDR4300
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config SYS_VENDOR
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default "tplink"
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config SYS_SOC
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default "ath79"
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config SYS_BOARD
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default "wdr4300"
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config SYS_CONFIG_NAME
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default "tplink_wdr4300"
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config SYS_TEXT_BASE
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default 0xa1000000
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config SYS_DCACHE_SIZE
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default 32768
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config SYS_DCACHE_LINE_SIZE
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default 32
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config SYS_ICACHE_SIZE
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default 65536
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config SYS_ICACHE_LINE_SIZE
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default 32
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endif
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