mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
15b8c75058
In order to fully support SPL_OF_CONTROL, we need BSS to be a bit larger. This patch relocates BSS to SDRAM instead of SRAM which is similar to how ARMv7 boards (like OMAP2+) do it. This means two new variables are required: CONFIG_SPL_BSS_START_ADDR set to DAVINCI_DDR_EMIF_DATA_BASE CONFIG_SPL_BSS_MAX_SIZE is set to 0x1080000 which is 1 byte before the location where U-Boot will load. Signed-off-by: Adam Ford <aford173@gmail.com>
66 lines
1.1 KiB
Plaintext
66 lines
1.1 KiB
Plaintext
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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*
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* (C) Copyright 2008
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* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
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*/
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MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
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LENGTH = CONFIG_SPL_MAX_FOOTPRINT }
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MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
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LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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ENTRY(_start)
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SECTIONS
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{
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. = 0x00000000;
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. = ALIGN(4);
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.text :
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{
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__start = .;
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*(.vectors)
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arch/arm/cpu/arm926ejs/start.o (.text*)
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*(.text*)
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} >.sram
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. = ALIGN(4);
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.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
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. = ALIGN(4);
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.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
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. = ALIGN(4);
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.u_boot_list : { KEEP(*(SORT(.u_boot_list*))); } >.sram
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. = ALIGN(4);
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.rel.dyn : {
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__rel_dyn_start = .;
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*(.rel*)
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__rel_dyn_end = .;
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} >.sram
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__image_copy_end = .;
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.end :
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{
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*(.__end)
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}
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_image_binary_end = .;
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.bss :
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{
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. = ALIGN(4);
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__bss_start = .;
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*(.bss*)
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. = ALIGN(4);
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__bss_end = .;
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} >.sdram
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}
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