mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-11 05:36:17 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
147 lines
3.0 KiB
C
147 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2011-2014 Panasonic Corporation
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* Copyright (C) 2015-2016 Socionext Inc.
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*/
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/printk.h>
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#include <time.h>
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#include "ddrphy-init.h"
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#include "ddrphy-regs.h"
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/* for LD4, Pro4, sLD8 */
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#define NR_DATX8_PER_DDRPHY 2
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void ddrphy_prepare_training(void __iomem *phy_base, int rank)
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{
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void __iomem *dx_base = phy_base + PHY_DX_BASE;
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int dx;
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u32 tmp;
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for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
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tmp = readl(dx_base + PHY_DX_GCR);
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/* Specify the rank that should be write leveled */
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tmp &= ~PHY_DX_GCR_WLRKEN_MASK;
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tmp |= (1 << (PHY_DX_GCR_WLRKEN_SHIFT + rank)) &
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PHY_DX_GCR_WLRKEN_MASK;
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writel(tmp, dx_base + PHY_DX_GCR);
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dx_base += PHY_DX_STRIDE;
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}
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tmp = readl(phy_base + PHY_DTCR);
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/* Specify the rank used during data bit deskew and eye centering */
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tmp &= ~PHY_DTCR_DTRANK_MASK;
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tmp |= (rank << PHY_DTCR_DTRANK_SHIFT) & PHY_DTCR_DTRANK_MASK;
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/* Use Multi-Purpose Register for DQS gate training */
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tmp |= PHY_DTCR_DTMPR;
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/* Specify the rank enabled for data-training */
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tmp &= ~PHY_DTCR_RANKEN_MASK;
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tmp |= (1 << (PHY_DTCR_RANKEN_SHIFT + rank)) & PHY_DTCR_RANKEN_MASK;
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writel(tmp, phy_base + PHY_DTCR);
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}
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struct ddrphy_init_sequence {
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char *description;
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u32 init_flag;
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u32 done_flag;
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u32 err_flag;
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};
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static const struct ddrphy_init_sequence init_sequence[] = {
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{
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"DRAM Initialization",
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PHY_PIR_DRAMRST | PHY_PIR_DRAMINIT,
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PHY_PGSR0_DIDONE,
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PHY_PGSR0_DIERR
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},
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{
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"Write Leveling",
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PHY_PIR_WL,
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PHY_PGSR0_WLDONE,
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PHY_PGSR0_WLERR
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},
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{
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"Read DQS Gate Training",
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PHY_PIR_QSGATE,
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PHY_PGSR0_QSGDONE,
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PHY_PGSR0_QSGERR
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},
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{
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"Write Leveling Adjustment",
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PHY_PIR_WLADJ,
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PHY_PGSR0_WLADONE,
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PHY_PGSR0_WLAERR
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},
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{
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"Read Bit Deskew",
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PHY_PIR_RDDSKW,
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PHY_PGSR0_RDDONE,
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PHY_PGSR0_RDERR
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},
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{
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"Write Bit Deskew",
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PHY_PIR_WRDSKW,
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PHY_PGSR0_WDDONE,
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PHY_PGSR0_WDERR
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},
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{
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"Read Eye Training",
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PHY_PIR_RDEYE,
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PHY_PGSR0_REDONE,
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PHY_PGSR0_REERR
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},
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{
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"Write Eye Training",
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PHY_PIR_WREYE,
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PHY_PGSR0_WEDONE,
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PHY_PGSR0_WEERR
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}
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};
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int ddrphy_training(void __iomem *phy_base)
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{
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int i;
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u32 pgsr0;
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u32 init_flag = PHY_PIR_INIT;
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u32 done_flag = PHY_PGSR0_IDONE;
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int timeout = 50000; /* 50 msec is long enough */
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#ifdef DEBUG
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ulong start = get_timer(0);
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#endif
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for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
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init_flag |= init_sequence[i].init_flag;
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done_flag |= init_sequence[i].done_flag;
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}
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writel(init_flag, phy_base + PHY_PIR);
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do {
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if (--timeout < 0) {
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pr_err("timeout during DDR training\n");
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return -ETIMEDOUT;
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}
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udelay(1);
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pgsr0 = readl(phy_base + PHY_PGSR0);
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} while ((pgsr0 & done_flag) != done_flag);
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for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
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if (pgsr0 & init_sequence[i].err_flag) {
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pr_err("%s failed\n", init_sequence[i].description);
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return -EIO;
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}
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}
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#ifdef DEBUG
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pr_debug("DDR training: elapsed time %ld msec\n", get_timer(start));
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#endif
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return 0;
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}
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