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https://github.com/brain-hackers/u-boot-brain
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e8cc3f04b1
Some TQM85xx boards could be equipped with up to 1 GiB (NOR) Flash memory. The current memory map only supports up to 128 MiB Flash. This patch adds the configuration option CONFIG_TQM_BIGFLASH. If set, up to 1 GiB flash is supported. To achieve this, the memory map has to be adjusted in great parts (for example the CCSRBAR is moved from 0xE0000000 to 0xA0000000). If you want to boot Linux with CONFIG_TQM_BIGFLASH set, the new memory map also has to be considered in the kernel (changed CCSRBAR address, changed PCI IO base address, ...). Please use an appropriate Flat Device Tree blob (tqm8548.dtb). Signed-off-by: Martin Krause <martin.krause@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
87 lines
3.1 KiB
C
87 lines
3.1 KiB
C
/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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/*
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* LAW(Local Access Window) configuration:
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*
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* Standard mapping:
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*
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* 0x0000_0000 0x7fff_ffff DDR 2G
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
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* 0xc000_0000 0xdfff_ffff RapidIO or PCI express 512M
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* 0xe000_0000 0xe000_ffff CCSR 1M
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* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
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* 0xe300_0000 0xe3ff_ffff CAN and NAND Flash 16M
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* 0xef00_0000 0xefff_ffff PCI express IO 16M
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* 0xfc00_0000 0xffff_ffff FLASH (boot bank) 128M
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*
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* Big FLASH mapping:
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*
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* 0x0000_0000 0x7fff_ffff DDR 2G
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
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* 0xa000_0000 0xa000_ffff CCSR 1M
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* 0xa200_0000 0xa2ff_ffff PCI1 IO 16M
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* 0xa300_0000 0xa3ff_ffff CAN and NAND Flash 16M
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* 0xaf00_0000 0xafff_ffff PCI express IO 16M
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* 0xb000_0000 0xbfff_ffff RapidIO or PCI express 256M
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* 0xc000_0000 0xffff_ffff FLASH (boot bank) 1G
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*
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* Notes:
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* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
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* If flash is 8M at default position (last 8M), no LAW needed.
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*/
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#ifdef CONFIG_TQM_BIGFLASH
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#define LAW_3_SIZE LAW_SIZE_1G
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#define LAW_5_SIZE LAW_SIZE_256M
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#else
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#define LAW_3_SIZE LAW_SIZE_128M
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#define LAW_5_SIZE LAW_SIZE_512M
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#endif
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struct law_entry law_table[] = {
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SET_LAW_ENTRY (1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
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SET_LAW_ENTRY (2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
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SET_LAW_ENTRY (3, CFG_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC),
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SET_LAW_ENTRY (4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
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#ifdef CONFIG_PCIE1
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SET_LAW_ENTRY (5, CFG_PCIE1_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1),
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#else /* !CONFIG_PCIE1 */
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SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO),
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#endif /* CONFIG_PCIE1 */
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#if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND)
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SET_LAW_ENTRY (6, CFG_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
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#endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */
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#ifdef CONFIG_PCIE1
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SET_LAW_ENTRY (7, CFG_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1),
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#endif /* CONFIG_PCIE */
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};
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int num_law_entries = ARRAY_SIZE (law_table);
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